These free resources are available to the Intel® Developer Network for PCI Express* Architecture community.
PCI Express* Specifications
The PHY Interface for the PCI Express* (PIPE) Architecture Gen 4 is a draft version of the PIPE spec that supports PCI Express* Gen 3, SATA and USB architectures. By downloading and reading the spec you agree to the obligations set forth in the Intel® Developer Network for PCI* Express Architecture user agreement. Comments can be sent to admin@pciexpressdevnet.org.
The PHY Interface for the PCI Express* (PIPE) Architecture Gen 3 Revision 0.9 is a draft version of the PIPE spec that supports PCI Express* Gen 3. The PIPE spec (PHY Interface for PCI Express* Architecture) describes a standardized interface between PCIe MAC implementations and PCIe PHY implementations. By downloading and reading the spec you agree to the obligations set forth in the Intel® Developer Network for PCI* Express Architecture user agreement. Comments can be sent to admin@pciexpressdevnet.org.
The PHY Interface for the PCI Express* Architecture (PIPE) for SATA 3.0 Revision 0.7 is a draft version of the PIPE spec that supports SATA 3.0. The PIPE spec (PHY Interface for PCI Express* Architecture) describes a standardized interface between SATA MAC implementations and SATA PHY implementations. By downloading and reading the spec you agree to the obligations set forth in the Intel® Developer Network for PCI* Express Architecture user agreement. Comments can be sent to admin@pciexpressdevnet.org.
The MAC-PHY Interface Connector for PCI Express* (PIPE) Architecture describes a standardized connector interface for discrete PHYs. The connector can handle PHYs with up to four lanes. The design is intended for prototyping/testing work, allowing MAC developers to be able to easily connect to PHYs from different vendors, and similarly provide an easy way for PHY vendors to try their designs with multiple MAC vendors.
White papers
- Atomic Read Modify Write Primitives for I/O Devices
- Merits of Data Reuse Hints
- PCI Express* (PCIe*) 3.0 Accelerator Features
- The Changing Nature of Data Center I/O
- I/O Considerations for Server Blades, Backplanes, and the Datacenter
- PCI Express* Provides Enterprise Reliability, Availability and Serviceability
- PCI Express* Technology: The Foundation of Enterprise Serial Innovation
- PCI Express* Architecture Power Management, Rev. 1.1
- PCI Express* to PCI-X* Bridge Architecture: Where Interface Standards Meet
- The Benefits of PCI Express* Architecture for Components and Systems
- Why PCI Express* Architecture for Graphics?
Tools
The Intel Channel Test Tool (ICTT) Version 1.0.0 is a beta version of the ICTT that supports PCI Express* Gen 3 Base and CEM specification simulations. ICTT will take input channels in .tr0 format and perform statistical system simulations showing the resulting eye diagram for add-in cards, motherboards, and base specification (chip to chip) channels. Comments, questions, and feature requests can be sent to admin@pciexpressdevnet.org
Single Root I/O Virtualization Resources
Single Root I/O Virtualization (IOV) lets multiple operating systems in a single computer to share PCI Express devices. Refer to the following for more information.
