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With industry leadership and innovation, Intel continues to support faster and more efficient data transfer by helping to define Serial ATA standards.
Intel® Universal Serial Bus (USB) enables easy, high-speed connections between peripherals and platforms. USB description, wireless, and future plans.
Intel® Universal Serial Bus (USB) Frequently Asked Questions (FAQ) about SuperSpeed USB 3.0, High-Speed USB 2.0, USB 2.0, & USB On-the-Go.
Technical details to understand USB 3.0 and 2.0 spec requirements, design compatible products, download developer-related PDFs, and more.
Intel® Universal Serial Bus (USB) overview, wireless USB, industry collaboration, and standards. For embedded developers.
The EHCI compliance testing evaluates the EHCI controller function of a USB 2.0 Host controller.
White Paper: Notice of certain USB 3.0* devices and cables causing radio frequency interference to wireless devices operating in the 2.4 GHz ISM band.
Information about the Enhanced Host Controller Interface specification, including licensing, revisions, addendums, and technical questions.
Specification: Describes the enhanced host controller interface for USB 2.0, including the system software/host controller hardware interface.
Answers to commonly asked questions about Intel® Data Direct I/O, including what is it, how does it work with other tech, and what does it benefit?
Technology Brief: improve direct I/O data processing efficiency for data delivery and consumption from I/O devices.
Written agreement of mutual promises and conditions between Intel and Contributor for contributing to the HCI Specification for Serial-ATA.
Programming register definitions, a method to detect support for direct software control, and a method for HW to autonomously enter and exit DevSleep.
White Paper: defines a PIPE connector interface to which MAC and PHY vendors can develop.
PCI Express* PHY Implementation for Intel Platforms includes encoding scheme, transmitter equalization and timing, and existing usage of K-code.
PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.
The Intel® Developer Network for PCI Express* Architecture is a developer community offering access to resources and peers.
White Paper: Power management guidelines for PCI Express* links on Intel®-based Mobile platforms.
Article: Hardware developer trends in enterprise interconnect technologies and how PCI Express* provides a common host connection attach point.
Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.
Design Guide, revision 1.63: for platform vendors, software developers and SATA device vendors to build power-friendly SATA-based platforms.
Thunderbolt™ technology is a single-cable, I/O technology for data transfers among multiple devices and device types that use different protocols.