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Serial ATA [57 K]
With industry leadership and innovation, Intel continues to support faster and more efficient data transfer by helping to define Serial ATA standards.

With industry leadership and innovation, Intel continues to support faster and more efficient data transfer by helping to define Serial ATA standards.

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USB (Universal Serial Bus) [58 K]
Intel® Universal Serial Bus (USB) enables easy, high-speed connections between peripherals and platforms. USB description, wireless, and future plans.

Intel® Universal Serial Bus (USB) enables easy, high-speed connections between peripherals and platforms. USB description, wireless, and future plans.

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Intel® Universal Serial Bus Frequently Asked Questions (FAQ) [58 K]
Intel® Universal Serial Bus (USB) Frequently Asked Questions (FAQ) about SuperSpeed USB 3.0, High-Speed USB 2.0, USB 2.0, & USB On-the-Go.

Intel® Universal Serial Bus (USB) Frequently Asked Questions (FAQ) about SuperSpeed USB 3.0, High-Speed USB 2.0, USB 2.0, & USB On-the-Go.

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Universal Serial Bus 3.0 and 2.0 Specifications [59 K]
Technical details to understand USB 3.0 and 2.0 spec requirements, design compatible products, download developer-related PDFs, and more.

Technical details to understand USB 3.0 and 2.0 spec requirements, design compatible products, download developer-related PDFs, and more.

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Intel® Universal Serial Bus Technology [62 K]
Intel® Universal Serial Bus (USB) overview, wireless USB, industry collaboration, and standards. For embedded developers.

Intel® Universal Serial Bus (USB) overview, wireless USB, industry collaboration, and standards. For embedded developers.

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Universal Serial Bus EHCI Compliance Testing Program [53 K]
The EHCI compliance testing evaluates the EHCI controller function of a USB 2.0 Host controller.

The EHCI compliance testing evaluates the EHCI controller function of a USB 2.0 Host controller.

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Why PCI Express* Architecture for Graphics?
White Paper: Intel® Developer Network for PCI Express* Architecture, benefits and graphics usages.

White Paper: Intel® Developer Network for PCI Express* Architecture, benefits and graphics usages.

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USB 3.0* Radio Frequency Interference on 2.4 GHz Devices
White Paper: Notice of certain USB 3.0* devices and cables causing radio frequency interference to wireless devices operating in the 2.4 GHz ISM band.

White Paper: Notice of certain USB 3.0* devices and cables causing radio frequency interference to wireless devices operating in the 2.4 GHz ISM band.

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Enhanced Host Controller Interface Specification [59 K]
Information about the Enhanced Host Controller Interface specification, including licensing, revisions, addendums, and technical questions.

Information about the Enhanced Host Controller Interface specification, including licensing, revisions, addendums, and technical questions.

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Enhanced Host Controller Interface for USB 2.0: Specification
Specification: Describes the enhanced host controller interface for USB 2.0, including the system software/host controller hardware interface.

Specification: Describes the enhanced host controller interface for USB 2.0, including the system software/host controller hardware interface.

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Intel® Data Direct I/O: Frequently Asked Questions
Answers to commonly asked questions about Intel® Data Direct I/O, including what is it, how does it work with other tech, and what does it benefit?

Answers to commonly asked questions about Intel® Data Direct I/O, including what is it, how does it work with other tech, and what does it benefit?

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Intel® Data Direct I/O Technology (Intel® DDIO): Technology Brief
Technology Brief: improve direct I/O data processing efficiency for data delivery and consumption from I/O devices.

Technology Brief: improve direct I/O data processing efficiency for data delivery and consumption from I/O devices.

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Serial ATA Host Controller Interface Spec: Contributor Agreement
Written agreement of mutual promises and conditions between Intel and Contributor for contributing to the HCI Specification for Serial-ATA.

Written agreement of mutual promises and conditions between Intel and Contributor for contributing to the HCI Specification for Serial-ATA.

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Serial ATA AHCI: Device Sleep Technical Proposal, Rev. 1.3.1
Programming register definitions, a method to detect support for direct software control, and a method for HW to autonomously enter and exit DevSleep.

Programming register definitions, a method to detect support for direct software control, and a method for HW to autonomously enter and exit DevSleep.

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Case Study: Intel PCI and PCI Express*
Case Study: Intel, PCI Express* 3.0, make the PC platform more functional, performance-balanced and responsive for a variety of applications.

Case Study: Intel, PCI Express* 3.0, make the PC platform more functional, performance-balanced and responsive for a variety of applications.

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MAC-PHY Interface Connector for the PCI Express* Architecture
White Paper: defines a PIPE connector interface to which MAC and PHY vendors can develop.

White Paper: defines a PIPE connector interface to which MAC and PHY vendors can develop.

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PCI Express* (PCIe*) 3.0 Accelerator Features
Summary of PCI Express* capabilities for revision 3.0 accelerator features of the specification.

Summary of PCI Express* capabilities for revision 3.0 accelerator features of the specification.

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PCI Express* 3.0: PHY Implementation for Intel Platforms
PCI Express* PHY Implementation for Intel Platforms includes encoding scheme, transmitter equalization and timing, and existing usage of K-code.

PCI Express* PHY Implementation for Intel Platforms includes encoding scheme, transmitter equalization and timing, and existing usage of K-code.

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PCI Express* [72 K]
PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

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PCI Express* Architecture [78 K]
The Intel® Developer Network for PCI Express* Architecture is a developer community offering access to resources and peers.

The Intel® Developer Network for PCI Express* Architecture is a developer community offering access to resources and peers.

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PCI Express* Architecture Power Management Rev 1.1
White Paper: Power management guidelines for PCI Express* links on Intel®-based Mobile platforms.

White Paper: Power management guidelines for PCI Express* links on Intel®-based Mobile platforms.

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PCI Express* Technology, Enterprise Serial Innovation
Article: Hardware developer trends in enterprise interconnect technologies and how PCI Express* provides a common host connection attach point.

Article: Hardware developer trends in enterprise interconnect technologies and how PCI Express* provides a common host connection attach point.

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PHY Interface for the PCI Express* Architecture: Revision .9
Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.

Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.

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Designing Energy Efficient SATA Devices: 2011-2013 Platforms
Design Guide, revision 1.63: for platform vendors, software developers and SATA device vendors to build power-friendly SATA-based platforms.

Design Guide, revision 1.63: for platform vendors, software developers and SATA device vendors to build power-friendly SATA-based platforms.

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Intel® Thunderbolt™ Technology Process Diagram [63 K]
Thunderbolt™ technology is a single-cable, I/O technology for data transfers among multiple devices and device types that use different protocols.

Thunderbolt™ technology is a single-cable, I/O technology for data transfers among multiple devices and device types that use different protocols.

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