White Paper discusses Intel® Microarchitecture (Nehalem), the basis for the Intel® Xeon® processor 3500 and 5500 series.
Powered by Intel® Xeon® processors, Intel® Rapid Storage Technology enterprise integrates SAS onto the chipset for reliable, cost-efficient storage.
Covers core code and services required for an implementation of the CPU I/O Protocol of the Intel® Platform Innovation Framework for EFI.
White Paper: Describes advantages of Aspera technology for ultra-high-speed data transfer in virtualized computing environments typical of the cloud.
Defines core code for an implementation of the Pre-EFI Initialization phase of the Intel® Platform Innovation Framework for EFI.
Validation results for DDR3 RDIMMS on Intel® Itanium® processor 9300-based motherboards.
This document describes the mechanisms by which the Intel® Platform Innovation Framework for EFI (the “Framework”) manages user input.
Defines the required core code and services for the Pre-EFI Initialization (PEI) phase of the Intel® Platform Innovation Framework for EFI.
Defines the core code and services required for implementation of the System Management Mode of the Intel® Platform Innovation Framework for EFI.
Supplier listing, 2010: Intel® Itanium® processor 9300 series enabling components.