第二代智能英特尔® 酷睿™ 处理器和赛扬® 处理器交互式结构图提供对功能、性能和连接性的说明。
White Paper: Provides platform-level error handling strategies and overview of error detection and notification capabilities. (v.001, May 2011)
BIOS Specification Update: Intel® 6/C200/C600 Series Chipset Platform Controller Hub (PCH) errata, clarifications, and changes. (v.001.3, Sept. 2012)
Application Note: SPI programming guide clarifies Serial Flash programming on Intel® 6 Series Express Chipset-based platforms. (v.001, July 2011)
BIOS Writer’s Guide: Assists with writing core BIOS code to support Sandy Bridge processor core-based systems. (v.001.6, June 2012)
BIOS Specification Update: Sandy Bridge System Agent device and document errata, spec clarifications, and spec changes. (v.001.2, July 2011)
User Specification: Intel® 6 Series Express Chipset Serial Flash overviews SPI sharing protocol, formatting, and considerations. (v.000.7, Aug. 2010)
Product Spec: Intel® Management Engine and embedded controller interaction and communication protocol for Huron River system. (v.000.7, Apr. 2010)