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MAC-PHY Interface Connector for the PCI Express* Architecture

White Paper: defines a PIPE connector interface to which MAC and PHY vendors can develop.

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PCI Express* Technology, Enterprise Serial Innovation

Article: Hardware developer trends in enterprise interconnect technologies and how PCI Express* provides a common host connection attach point.

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PCI Express* 3.0: Electrical Requirements for Designing ASICs

Presentation: PCI Express* Electrical Requirements for Designing ASICs on Intel Platforms covers background, Silicon TX, silicon RX test, and more.

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PCI Express* 3.0: Optimize Device Architecture on Intel Platforms

Presentation: PCI Express* protocol extensions summary, device architecture considerations, and software development.

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PHY Interface For the PCI Express* Architecture

Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.

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PHY Interface for the PCI Express* and USB SuperSpeed Architectures

Specification: PHY interface for PCI Express* and USB SuperSpeed*, enables development of functionally equivalent PCI Express and USB SuperSpeed PHYs.

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Thunderbolt™ Technology

Thunderbolt™ technology is a single-cable, I/O technology for data transfers among multiple devices and device types that use different protocols.

Universal Serial Bus EHCI Compliance Testing Program

The EHCI compliance testing evaluates the EHCI controller function of a USB 2.0 Host controller.

USB 3.0 Internal Connector and Cable Specification

Internal cable interface for USB 3.0 in desktops, focuses on electrical and mechanical requirements of the connector and cable assembly.

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Intel® Many Integrated Core Architecture - Advanced

Intel® Many Integrated Core (Intel® MIC) architecture is the latest breakthrough in supercomputing speed, performance, and compatibility.