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Enhanced Host Controller Interface Specification [50 K]
Information about the Enhanced Host Controller Interface specification, including licensing, revisions, addendums, and technical questions.

Information about the Enhanced Host Controller Interface specification, including licensing, revisions, addendums, and technical questions.

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Enhanced Host Controller Interface for USB 2.0: Specification
Specification: Describes the enhanced host controller interface for USB 2.0, including the system software/host controller hardware interface.

Specification: Describes the enhanced host controller interface for USB 2.0, including the system software/host controller hardware interface.

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Thunderbolt™ Technology [54 K]
Thunderbolt™ technology is a single-cable, I/O technology for data transfers among multiple devices and device types that use different protocols.

Thunderbolt™ technology is a single-cable, I/O technology for data transfers among multiple devices and device types that use different protocols.

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USB (Universal Serial Bus) [49 K]
Intel® Universal Serial Bus (USB) enables easy, high-speed connections between peripherals and platforms. USB description, wireless, and future plans.

Intel® Universal Serial Bus (USB) enables easy, high-speed connections between peripherals and platforms. USB description, wireless, and future plans.

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Universal Serial Bus EHCI Compliance Testing Program [44 K]
The EHCI compliance testing evaluates the EHCI controller function of a USB 2.0 Host controller.

The EHCI compliance testing evaluates the EHCI controller function of a USB 2.0 Host controller.

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Intel® Data Direct I/O: Frequently Asked Questions
Answers to commonly asked questions about Intel® Data Direct I/O, including what is it, how does it work with other tech, and what does it benefit?

Answers to commonly asked questions about Intel® Data Direct I/O, including what is it, how does it work with other tech, and what does it benefit?

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Intel® Data Direct I/O Technology Chalk Talk Video [63 K]
This chalk talk video describes the features and performance benefits of Intel® DDIO for Intel® Ethernet products.

This chalk talk video describes the features and performance benefits of Intel® DDIO for Intel® Ethernet products.

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PCI Express* Architecture [74 K]
The Intel® Developer Network for PCI Express* Architecture is a developer community offering access to resources and peers.

The Intel® Developer Network for PCI Express* Architecture is a developer community offering access to resources and peers.

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PCI Express* [51 K]
PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

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PCI Express* Architecture [52 K]
PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

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PCI Express* Architecture Resources [47 K]
Get additional information about the PCI Express* architecture with a white paper, developer’s guide, and community resources.

Get additional information about the PCI Express* architecture with a white paper, developer’s guide, and community resources.

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PHY Interface For the PCI Express* Architecture
Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.

Specification: PHY interface for PCI Express* Architecture (PIPE), enables development of functionally equivalent PCI Express PHYs, for SATA 3.0.

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PCI Express* 3.0: Optimize Device Architecture on Intel Platforms
Presentation: PCI Express* protocol extensions summary, device architecture considerations, and software development.

Presentation: PCI Express* protocol extensions summary, device architecture considerations, and software development.

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PCI Express* 3.0: Electrical Requirements for Designing ASICs
Presentation: PCI Express* Electrical Requirements for Designing ASICs on Intel Platforms covers background, Silicon TX, silicon RX test, and more.

Presentation: PCI Express* Electrical Requirements for Designing ASICs on Intel Platforms covers background, Silicon TX, silicon RX test, and more.

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PHY Interface for the PCI Express* and USB SuperSpeed Architectures
Specification: PHY interface for PCI Express* and USB SuperSpeed*, enables development of functionally equivalent PCI Express and USB SuperSpeed PHYs.

Specification: PHY interface for PCI Express* and USB SuperSpeed*, enables development of functionally equivalent PCI Express and USB SuperSpeed PHYs.

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PCI Express* Technology, Enterprise Serial Innovation
Article: Hardware developer trends in enterprise interconnect technologies and how PCI Express* provides a common host connection attach point.

Article: Hardware developer trends in enterprise interconnect technologies and how PCI Express* provides a common host connection attach point.

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MAC-PHY Interface Connector for the PCI Express* Architecture
White Paper: defines a PIPE connector interface to which MAC and PHY vendors can develop.

White Paper: defines a PIPE connector interface to which MAC and PHY vendors can develop.

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USB 3.0 Internal Connector and Cable Specification
Internal cable interface for USB 3.0 in desktops, focuses on electrical and mechanical requirements of the connector and cable assembly.

Internal cable interface for USB 3.0 in desktops, focuses on electrical and mechanical requirements of the connector and cable assembly.

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Serial ATA Host Controller Interface Spec: Contributor Agreement
Written agreement of mutual promises and conditions between Intel and Contributor for contributing to the HCI Specification for Serial-ATA.

Written agreement of mutual promises and conditions between Intel and Contributor for contributing to the HCI Specification for Serial-ATA.

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Serial ATA AHCI: Specification Draft, Rev. 0.95
Defines functional behavior and Advanced Host Controller Interface software for moving data between system memory and serial ATA devices.

Defines functional behavior and Advanced Host Controller Interface software for moving data between system memory and serial ATA devices.

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Serial ATA AHCI: Specification, Rev. 1.1
Defines functional behavior and Advanced Host Controller Interface software for moving data between system memory and serial ATA devices.

Defines functional behavior and Advanced Host Controller Interface software for moving data between system memory and serial ATA devices.

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Serial ATA AHCI: Specification, Rev. 1.2
Defines functional behavior and Advanced Host Controller Interface software for moving data between system memory and serial ATA devices.

Defines functional behavior and Advanced Host Controller Interface software for moving data between system memory and serial ATA devices.

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Serial ATA AHCI: Specification, Rev. 1.3
Defines functional behavior and Advanced Host Controller Interface software for moving data between system memory and serial ATA devices.

Defines functional behavior and Advanced Host Controller Interface software for moving data between system memory and serial ATA devices.

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Serial ATA AHCI: Device Sleep Technical Proposal, Rev. 1.3.1
Programming register definitions, a method to detect support for direct software control, and a method for HW to autonomously enter and exit DevSleep.

Programming register definitions, a method to detect support for direct software control, and a method for HW to autonomously enter and exit DevSleep.

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Serial ATA Frequently Asked Questions (FAQ) [66 K]
Serial ATA frequently asked questions from hardware developers concerning general I/O acceleration in storage systems.

Serial ATA frequently asked questions from hardware developers concerning general I/O acceleration in storage systems.

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