--------------------------------------------------------------------------
-- Boundary-Scan Description Language (BSDL) enhancement file 
-- Manufacturer: Intel Corporation
-- Component   : Intel(R) C600 Series Chipset
-- SKU         : C602(-A),C604(-B),C606(-D),C608(-T) and C602J(-J)
-- Package(s)  : bga 
-- Version     : 2.0
-- Date        : Monday Feb 06 2012 14:38:47
-- Entity name : pbg_C1_bsdl
-- Description : Intel(R) C600 Series Chipset Family Logic File
--------------------------------------------------------------------------
-- Information in this document is provided in connection with Intel products.
-- No license, express or implied, by estoppel or otherwise, to any
-- intellectual property rights is granted by this document. Except as
-- provided in Intel's Terms and Conditions of Sale for such products,
-- Intel assumes no liability whatsoever, and Intel disclaims any express or
-- implied warranty, relating to sale and/or use of Intel products including
-- liability or warranties relating to fitness for a particular purpose,
-- merchantability, or infringement of any patent, copyright or other
-- intellectual property right. Intel products are not intended for use in
-- medical, life saving, or life sustaining applications.
--
-- Intel may make changes to specifications and product descriptions at any
-- time, without notice.
--
-- This product may contain design defects or errors 
-- known as errata which may cause the product to deviate from published
-- specifications. Current characterized errata are available on request.
--
-- Contact your local Intel sales office or your distributor to obtain the
-- latest specifications and before placing your product order.
--
-- Copyright (c) Intel Corporation 2012. Third-party brands and names are the
-- property of their respective owners.
-------------------------------------------------------------------------------------------
-- Revision History:
-- 7-17-2010 Rev. 1.0 Initial Release
-- 2-19-2011 Rev. 1.2 Supports B0 steppings.
-- 7-15-2011 Rev. 1.5 Supports C0 steppings.
--                    Changed PWROK to PCH_PWROK to match all documents.
--                    Changed PERN1-PERN8, PERP1-PERP8, PETN1-PETN8, PETP1-PETP8,
--                            PROCPWRGD, SST to V1_1 logic from V3_3.
--                    Changed PM_SYNC, PM_SYNC2 to V1_1 logic from V1_2.  
--                    Changed DF_TVS from NC to IO.
--                    Changed CLKIN_PCI to V3_3 logic from V1_1 logic.
-- 11-29-2011 Rev.1.8 Supports C1 stepppings.  
-- 02-06-2012 Rev.2.0 Updated for final release. 
-------------------------------------------------------------------------------------------

begin family V3_3 default	
  vih 3.0	
  vil 0	
  voh 0.7*vcc33	
  vol 0.3*vcc33	
end	
	
begin family V1_8	
  vih 1.8	
  vil 0	
  voh vcc18-0.4	
  vol 0.4	
end	
	
begin family V1_5	
  vih 1.5	
  vil 0	
  voh 0.9*vcc15	
  vol 0.1*vcc15	
end	
	
begin family V1_2	
  vih 1.2	
  vil 0.0	
  voh 0.8	
  vol 0.6	
end	
	
begin family V1_1	
  vih 1.1	
  vil 0	
  voh 0.9	
  vol 0.15		
end		
		
begin	pin	
B26	A20GATE	I	
AW15	AD_0	IO	
AA30	AD_1	IO	
AC32	AD_10	IO	
AW20	AD_11	IO	
AM18	AD_12	IO	
AP12	AD_13	IO	
AL31	AD_14	IO	
AM30	AD_15	IO	
AM25	AD_16	IO	
AU22	AD_17	IO	
AG30	AD_18	IO	
AG32	AD_19	IO	
AN15	AD_2	IO	
AN34	AD_20	IO	
AK33	AD_21	IO	
AL21	AD_22	IO	
AK27	AD_23	IO	
AM24	AD_24	IO	
AV13	AD_25	IO	
AD32	AD_26	IO	
AL34	AD_27	IO	
AR33	AD_28	IO	
AG31	AD_29	IO	
AR36	AD_3	IO	
AL30	AD_30	IO	
AA31	AD_31	IO	
AP36	AD_4	IO	
AV14	AD_5	IO	
Y30	AD_6	IO	
AU12	AD_7	IO	
AU25	AD_8	IO	
AW12	AD_9	IO	
H37	ADR_COMPLETE	O	
F33	APWROK	I	
E24	BMBUSY#/GPIO0	IO	
B2	CHIP_DETECT#	NC	
M1	CLKIN_DMI_N	I	V1_1
M2	CLKIN_DMI_P	I	V1_1
R32	CLKIN_DOT96N	I	V1_1
R31	CLKIN_DOT96P	I	V1_1
AK22	CLKIN_PCI	I
AU28	CLKIN_SAS0N	I	V1_1
AV27	CLKIN_SAS0P	I	V1_1
AV33	CLKIN_SAS1N	I	V1_1
AW33	CLKIN_SAS1P	I	V1_1
B17	CLKIN_SATA_N	I	V1_1
A17	CLKIN_SATA_P	I	V1_1
AN1	CLKIN_SPCIE0N	I	V1_1
AM2	CLKIN_SPCIE0P	I	V1_1
AM31	C/BE0#	IO	
AL18	C/BE1#	IO	
AL33	C/BE2#	IO	
AU20	C/BE3#	IO	
M28	DcpRTC	P	
L25	DcpSST	P	
N26	DcpSus	P	
U15	DcpSus	P	
U16	DcpSus	P	
L26	DcpSusByp	P	
AJ32	DEVSEL#	IO	
U12	DMI_RCOMP	I	V1_1
U5	DMI_RXN_0	IO	V1_1
T6	DMI_RXN_1	IO	V1_1
P4	DMI_RXN_2	IO	V1_1
N5	DMI_RXN_3	IO	V1_1
U6	DMI_RXP_0	IO	V1_1
T5	DMI_RXP_1	IO	V1_1
P5	DMI_RXP_2	IO	V1_1
N4	DMI_RXP_3	IO	V1_1
V2	DMI_TXN_0	O	V1_1
U1	DMI_TXN_1	O	V1_1
R2	DMI_TXN_2	O	V1_1
R1	DMI_TXN_3	O	V1_1
U3	DMI_TXP_0	O	V1_1
U2	DMI_TXP_1	O	V1_1
R3	DMI_TXP_2	O	V1_1
P2	DMI_TXP_3	O	V1_1
U13	DMI_ZCOMP	I	V1_1
U9	DMIRBIAS	ND	
R37	DPWROK	I	
J28	DRAMPWROK	OD	
R39	DSWODVREN	I	
AF31	FRAME#	IO	
AN33	GNT0#	IO	
AU15	GNT1#/GPIO51/GSXDOUT	IO	
AJ34	GNT2#/GPIO53/GSXDIN	IO	
AF30	GNT3#/GPIO55	IO	
AV24	GPIO13	IO	
E30	GPIO15	IO	
B29	GPIO18	IO	
F24	SMI#/GPIO20	IO	
F34	GPIO24	IO	
J38	GPIO25	IO	
F31	GPIO26	IO	
M35	GPIO27	IO	
A33	GPIO28	IO	
K33	GPIO31/MGPIO2	IO	
B24	GPIO32	IO	
AT37	GPIO33	IO	
F25	GPIO34	IO	
B31	NMI#/GPIO35	IO	
J25	GPIO44	IO	
E25	GPIO45	IO	
D37	GPIO46	IO	
B32	GPIO47	IO	
H27	GPIO56	IO	
J27	GPIO57	IO	
AL16	GPIO64	IO	
AK16	GPIO65	IO	
AL15	GPIO66	IO	
AK15	GPIO67	IO	
E38	GPIO72	IO	
B33	GPIO73	IO	
F38	GPIO8	IO	
V29	HDA_BCLK	IO	
AW22	HDA_RST#	IO	
AH37	HDA_SDIN_0	IO	
AG38	HDA_SDIN_1	IO	
AH39	HDA_SDIN_2	IO	
AH38	HDA_SDIN_3	IO	
V30	HDA_SDO	IO	
AV17	HDA_SYNC	IO	
C31	INIT3_3V#	IO	
P34	INTRUDER#	I	
M34	INTVRMEN	I	
AP18	IRDY#	IO	
A37	JTAG_TCK	I	V1_1
E28	JTAG_TDI	I	V1_1
A34	JTAG_TDO	OD	V1_1
C39	JTAG_TMS	I	V1_1
AV15	LAD_0	IO	
AV23	LAD_1	IO	
AL36	LAD_2	IO	
AU17	LAD_3	IO	
F39	LAN_PHY_PWR_CTRL/GPIO12	IO	
AP19	LDRQ0#	I	
AR37	LDRQ1#/GPIO23	IO	
AF36	LFRAME#	IO	
E13	TS_VSS1	NC	
H16	TS_VSS2	NC	
E12	TS_VSS3	NC	
H15	TS_VSS4	NC	
AP13	NC_1	NC	
B38	NC_2	NC	
AV38	NC_3	NC	
AV2	NC_4	NC	
A7	Reserved	NC	
B6	Reserved	NC	
C5	Reserved	NC	
E7	Reserved	NC	
J4	Reserved	NC	
C7	DF_TVS	IO	
F12	Reserved	NC	
K6	Reserved	NC	
J13	Reserved	NC	
E10	Reserved	NC	
F7	Reserved	NC	
F6	Reserved	NC	
H9	Reserved	NC	
K7	Reserved	NC	
L12	Reserved	NC	
H10	Reserved	NC	
K13	Reserved	NC	
E9	Reserved	NC	
F13	Reserved	NC	
J12	Reserved	NC	
F9	Reserved	NC	
F10	Reserved	NC	
L13	Reserved	NC	
K12	Reserved	NC	
B5	Reserved	NC	
B8	Reserved	NC	
F4	Reserved	NC	
E6	Reserved	NC	
C10	Reserved	NC	
J10	Reserved	NC	
K2	NC_5	NC	
N9	NC_6	NC	
E2	NC_7	NC	
F2	NC_8	NC	
L8	NC_9	NC	
N12	NC_10	NC	
E3	NC_11	NC	
L6	NC_12	NC	
D3	NC_13	NC	
K1	NC_14	NC	
J2	NC_15	NC	
L5	NC_16	NC	
N8	NC_17	NC	
G3	NC_18	NC	
H2	NC_19	NC	
L9	NC_20	NC	
N11	NC_21	NC	
G1	NC_22	NC	
C3	NC_23	NC	
K3	NC_24	NC	
K34	OC0#/GPIO59	IO	
M37	OC1#/GPIO40	IO	
M38	OC2#/GPIO41	IO	
K36	OC3#/GPIO42	IO	
J30	OC4#/GPIO43	IO	
L39	OC5#/GPIO9	IO	
K30	OC6#/GPIO10	IO	
K38	OC7#/GPIO14	IO	
AK28	PAR	IO	
R34	PCH_PWROK	I	
AE4	PERN1	IO      V1_1	
AF5	PERN2	IO	V1_1
AH6	PERN3	IO	V1_1
AJ6	PERN4	IO	V1_1
AE8	PERN5	IO	V1_1
AF8	PERN6	IO	V1_1
AH8	PERN7	IO	V1_1
AJ9	PERN8	IO	V1_1
AE5	PERP1	IO	V1_1
AF4	PERP2	IO	V1_1
AH5	PERP3	IO	V1_1
AJ5	PERP4	IO	V1_1
AE9	PERP5	IO	V1_1
AF9	PERP6	IO	V1_1
AH9	PERP7	IO	V1_1
AJ8	PERP8	IO	V1_1
AB1	PETN1	O	V1_1
AC2	PETN2	O	V1_1
AE1	PETN3	O	V1_1
AF2	PETN4	O	V1_1
AH1	PETN5	O	V1_1
AH2	PETN6	O	V1_1
AK1	PETN7	O	V1_1
AL2	PETN8	O	V1_1
AB2	PETP1	O	V1_1
AB3	PETP2	O	V1_1
AD2	PETP3	O	V1_1
AE3	PETP4	O	V1_1
AG2	PETP5	O	V1_1
AH3	PETP6	O	V1_1
AJ2	PETP7	O	V1_1
AK3	PETP8	O	V1_1
E33	PCIRST#	IO	
E4	PECI	IO	V1_2
AL5	PEG0_RBIASN	ND	
AL4	PEG0_RBIASP	ND	
AU3	PEG0_RN_0	IO	V1_1
AV5	PEG0_RN_1	IO	V1_1
AU7	PEG0_RN_2	IO	V1_1
AV8	PEG0_RN_3	IO	V1_1
AT3	PEG0_RP_0	IO	V1_1
AU5	PEG0_RP_1	IO	V1_1
AV6	PEG0_RP_2	IO	V1_1
AW7	PEG0_RP_3	IO	V1_1
AP3	PEG0_TN_0	O	V1_1
AR4	PEG0_TN_1	O	V1_1
AP6	PEG0_TN_2	O	V1_1
AR7	PEG0_TN_3	O	V1_1
AN3	PEG0_TP_0	O	V1_1
AN4	PEG0_TP_1	O	V1_1
AR6	PEG0_TP_2	O	V1_1
AP7	PEG0_TP_3	O	V1_1
AM19	PERR#	IO	
AR19	PIRQA#	IOD	
AJ30	PIRQB#	IOD	
AV18	PIRQC#	IOD	
AR18	PIRQD#	IOD	
AF32	PIRQE#/GPIO2	IO	
AL22	PIRQF#/GPIO3	IO	
AA32	PIRQG#/GPIO4	IO	
AR16	PIRQH#/GPIO5	IO	
AR15	PLOCK#	IO	
E34	PLTRST#	IO	
J6	PM_SYNC	IO	v1_1
H4	PM_SYNC2	IO	v1_1	
C37	PME#	IOD	
J9	PROCPWRGD	IO      V1_1	
AW17	PWM0	O	
AV22	PWM1	O	
AR13	PWM2	O	
AG36	PWM3	O	
K31	PWRBTN#	I	
B14	SATA3RRBIAS	ND	
B28	RCIN#	I	
AV12	REFCLK14IN	I	
AL27	REQ0#	IO	
AR34	REQ1#/GPIO50/GSXCLK	IO	
AK34	REQ2#/GPIO52/GSXSLOAD	IO	
AK21	REQ3#/GPIO54/GSXSRESET#	IO	
AA2	Reserved	NC	
AB5	Reserved	NC	
AB6	Reserved	NC	
AC5	Reserved	NC	
AC6	Reserved	NC	
W2	Reserved	NC	
Y1	Reserved	NC	
Y3	Reserved	NC	
Y4	CLKIN_GND0_P	I	V1_1
Y5	CLKIN_GND0_N	I	V1_1
G39	RI#	I	
M30	RSMRST#	I	
R38	RTCRST#	I	
R36	RTCX1	I	
P36	RTCX2	I	
AL8	SAS_CLOCK1	IOD	
AW10	SAS_CLOCK2	IOD	
AL9	SAS_DATAIN1	IOD	
AU10	SAS_DATAIN2	IOD	
AV9	SAS_DATAOUT1	IOD	
AR10	SAS_DATAOUT2	IOD	
AR9	SAS_LED#	IOD	
AN10	SAS_LOAD1	IOD	
AV10	SAS_LOAD2	IOD	
AW25	SAS_RBIASN_0	ND	
AL24	SAS_RBIASN_1	ND	
AV26	SAS_RBIASP_0	ND	
AL25	SAS_RBIASP_1	ND	
AR21	SAS0RXN	IO	V1_1
AR22	SAS1RXN	IO	V1_1
AP24	SAS2RXN	IO	V1_1
AP25	SAS3RXN	IO	V1_1
AN27	SAS4RXN	IO	V1_1
AN28	SAS5RXN	IO	V1_1
AP30	SAS6RXN	IO	V1_1
AP31	SAS7RXN	IO	V1_1
AN21	SAS0RXP	IO	V1_1
AN22	SAS1RXP	IO	V1_1
AR24	SAS2RXP	IO	V1_1
AR25	SAS3RXP	IO	V1_1
AR27	SAS4RXP	IO	V1_1
AR28	SAS5RXP	IO	V1_1
AR30	SAS6RXP	IO	V1_1
AR31	SAS7RXP	IO	V1_1
AJ12	SASSMBCLK0	O	
AH13	SASSMBCLK1	O	
AL13	SASSMBCLK2	O	
AL11	SASSMBDATA0	IO	
AH12	SASSMBDATA1	IO	
AM13	SASSMBDATA2	IO	
AW28	SAS0TXN	O	V1_1
AV29	SAS1TXN	O	V1_1
AW30	SAS2TXN	O	V1_1
AV32	SAS3TXN	O	V1_1
AN38	SAS4TXN	O	V1_1
AN39	SAS5TXN	O	V1_1
AL38	SAS6TXN	O	V1_1
AK39	SAS7TXN	O	V1_1
AV28	SAS0TXP	O	V1_1
AU30	SAS1TXP	O	V1_1
AV31	SAS2TXP	O	V1_1
AU33	SAS3TXP	O	V1_1
AN37	SAS4TXP	O	V1_1
AM38	SAS5TXP	O	V1_1
AK37	SAS6TXP	O	V1_1
AJ38	SAS7TXP	O	V1_1
E15	SATA0RXN	IO	V1_1
E16	SATA1RXN	IO	V1_1
E18	SATA2RXN	IO	V1_1
E19	SATA3RXN	IO	V1_1
E21	SATA4RXN	IO	V1_1
E22	SATA5RXN	IO	V1_1
F15	SATA0RXP	IO	V1_1
F16	SATA1RXP	IO	V1_1
F18	SATA2RXP	IO	V1_1
F19	SATA3RXP	IO	V1_1
F21	SATA4RXP	IO	V1_1
F22	SATA5RXP	IO	V1_1
A12	SATA0TXN	O	V1_1
B13	SATA1TXN	O	V1_1
B18	SATA2TXN	O	V1_1
A20	SATA3TXN	O	V1_1
B21	SATA4TXN	O	V1_1
A22	SATA5TXN	O	V1_1
B12	SATA0TXP	O	V1_1
C12	SATA1TXP	O	V1_1
C17	SATA2TXP	O	V1_1
B19	SATA3TXP	O	V1_1
C20	SATA4TXP	O	V1_1
B22	SATA5TXP	O	V1_1
J24	SATA0GP/GPIO21	IO	
A25	SATA1GP/GPIO19	IO	
C25	SATA2GP/GPIO36	IO	
C15	SATA3COMPI	I	V1_1
J16	SATA3COMPO	I	V1_1
C28	SATA3GP/GPIO37	IO	
H22	SATA4GP/GPIO16	IO	
H21	SATA5GP/GPIO49	IO	
K18	SATAICOMPI	I	V1_1
J18	SATAICOMPO	I	V1_1
B27	SATALED#	IOD	
F27	SCLOCK/GPIO22	IO	
K25	SDATAOUT0/GPIO39	IO	
E27	SDATAOUT1/GPIO48	IO	
C22	SERIRQ	IO	
AN16	SERR#	IO	
A30	SLOAD/GPIO38	IO	
E37	SLP_A#	IO	
H28	SLP_LAN#/GPIO29	IO	
F30	SLP_S3#	IO	
E31	SLP_S4#	IO	
B35	SLP_S5#/GPIO63	IO	
M39	SLP_SUS#	IO	
J31	SMBALERT#/GPIO11	IO	
G37	SMBCLK	IOD	
H38	SMBDATA	IOD	
H34	SML0ALERT#/GPIO60	IO	
F36	SML0CLK	IOD	
G36	SML0DATA	IOD	
J33	SML1ALERT#/GPIO74	IO	
K37	SML1CLK/GPIO58	IO	
K39	SML1DATA/GPIO75	IO	
B23	SPI_CLK	IO	
K19	SPI_CS0#	IO	
J21	SPI_CS1#	IO	
J22	SPI_MISO	IO	
K24	SPI_MOSI	IO	
A28	SPKR	IO	
P38	SRTCRST#	IO	
J34	SST	IO	V1_1
AV19	STOP#	IO	
E36	GPIO61	IO	
H33	SUSACK#	I	
C35	SUSCLK/GPIO62	IO	
N38	SUSWARN#/SUSPWRDNACK/GPIO30	IO	
C33	SYS_PWROK	I	
C30	SYS_RESET#	I	
AV21	TACH0/GPIO17	IO	
AL19	TACH1/GPIO1	IO	
Y31	TACH2/GPIO6	IO	
AJ35	TACH3/GPIO7	IO	
AG34	TACH4/GPIO68	IO	
Y32	TACH5/GPIO69	IO	
AF34	TACH6/GPIO70	IO	
AM36	TACH7/GPIO71	IO	
J7	THRMTRIPB	I	
W4	TP1	ND	
AU1	TP10	NC	
AL28	TP11	ND	
F28	TP12	NC	
AU37	TP13	ND	
AU39	TP14	ND	
AV35	TP15	ND	
AT39	TP16	ND	
AU35	TP17	NC	
AR38	TP18	NC	
B10	TP19	NC	
W5	TP2	ND	
A15	TP20	ND	
J19	TP21	ND	
B15	TP22	ND	
P32	TP23	NC	
P31	TP24	NC	
U8	TP3	ND	
P11	TP4	ND	
P9	TP5	ND	
M32	TP6	NC	
AN2	TP7	ND	
AT1	TP8	ND	
AP1	TP9	NC	
AR12	TRDY#	IO	
U38	USBN_0	IO	
W38	USBN_1	IO	
AD34	USBN_10	IO	
AC34	USBN_11	IO	
AA34	USBN_12	IO	
Y34	USBN_13	IO	
U37	USBN_2	IO	
Y37	USBN_3	IO	
AB38	USBN_4	IO	
AB37	USBN_5	IO	
AD38	USBN_6	IO	
AE37	USBN_7	IO	
U34	USBN_8	IO	
V34	USBN_9	IO	
U39	USBP_0	IO	
Y39	USBP_1	IO	
AD35	USBP_10	IO	
AC35	USBP_11	IO	
AA36	USBP_12	IO	
Y36	USBP_13	IO	
V38	USBP_2	IO	
AA38	USBP_3	IO	
AB39	USBP_4	IO	
AC38	USBP_5	IO	
AE39	USBP_6	IO	
AF38	USBP_7	IO	
U35	USBP_8	IO	
V35	USBP_9	IO	
V32	USBRBIASn	ND	V1_1
U32	USBRBIASp	ND	V1_1
L16	V_PROC_IO	P	
AC16	vccCore	P	
AC17	vccCore	P	
AC18	vccCore	P	
AC19	vccCore	P	
AC20	vccCore	P	
AD16	vccCore	P	
AD17	vccCore	P	
AD18	vccCore	P	
AD19	vccCore	P	
AD20	vccCore	P	
J15	vccCore	P	
N15	vccCore	P	
N16	vccCore	P	
T17	vccCore	P	
T18	vccCore	P	
T19	vccCore	P	
T20	vccCore	P	
U17	vccCore	P	
U18	vccCore	P	
U19	vccCore	P	
U20	vccCore	P	
W16	vccCore	P	
W17	vccCore	P	
W18	vccCore	P	
W19	vccCore	P	
W20	vccCore	P	
Y16	vccCore	P	
Y17	vccCore	P	
Y18	vccCore	P	
Y19	vccCore	P	
Y20	vccCore	P	
L15	VccDMI	P	
AB12	VccIO	P	
AB13	VccIO	P	
AB8	VccIO	P	
AB9	VccIO	P	
AC12	VccIO	P	
AC13	VccIO	P	
AC8	VccIO	P	
AC9	VccIO	P	
AE11	VccIO	P	
AE24	VccIO	P	
AF11	VccXUS	P	
AF12	VccXUS	P	
AF16	VccXUS	P	
AF17	VccXUS	P	
AF20	Vcc_RBIAS_SAS0	P	
AF24	VccIO	P	
AF25	VccIO	P	
AF26	VccIO	P	
AF28	VccIO	P	
AH15	VccXUS	P	
AH16	VccXUS	P	
AH23	Vcc_RBIAS_SAS1	P	
AH25	VccIO	P	
AH26	VccIO	P	
AH28	VccIO	P	
AJ13	Vcc_RBIAS_PU	P	
AJ15	VccXUS	P	
AJ16	VccXUS	P	
AJ23	Vcc_RBIAS_SAS1	P	
AJ25	VccIO	P	
AJ26	VccIO	P	
AJ28	VccIO	P	
AN9	VccXUS	P	
AR2	VccXUS	P	
L19	VccIO	P	
L23	VccIO	P	
M19	VccIO	P	
M24	VccIO	P	
N20	VccIO	P	
N23	VccIO	P	
N24	VccIO	P	
P12	VccIO	P	
T12	VccIO	P	
T13	VccIO	P	
T16	VccIO	P	
W11	VccIO	P	
W12	VccIO	P	
W15	VccIO	P	
Y11	VccIO	P	
Y12	VccIO	P	
Y15	VccIO	P	
Y25	VccIO	P	
Y26	VccIO	P	
Y28	VccIO	P	
Y9	VccIO	P	
L17	VccVRM	P	
L20	VccVRM	P	
AC29	vcc3_3	P	
AC30	vcc3_3	P	
AH18	vcc3_3	P	
AJ18	vcc3_3	P	
L24	vcc3_3	P	
N22	vcc3_3	P	
R22	vcc3_3	P	
T8	Vcc3_3	P	
AD29	V5REF	P	
U28	V5REF_Sus	P	
Y8	VCCAPLLDMI2	P	
P8	VccAPLLEXP	P	
M20	VccAPLLSATA	P	
AC25	VccASW	P	
AC26	VccASW	P	
AC28	VccASW	P	
AD25	VccASW	P	
AD26	VccASW	P	
AD28	VccASW	P	
T22	VccASW	P	
T23	VccASW	P	
T24	VccASW	P	
T26	VccASW	P	
T28	VccASW	P	
U22	VccASW	P	
U23	VccASW	P	
U24	VccASW	P	
U26	VccASW	P	
V24	VccASW	P	
W22	VccASW	P	
W23	VccASW	P	
W24	VccASW	P	
Y22	VccASW	P	
Y23	VccASW	P	
Y24	VccASW	P	
U29	VccAUBG	P	
M25	VccAUPLL	P	
N28	VccDSW3_3	P	
L18	VccDFTERM	P	
M18	VccDFTERM	P	
N17	VccDFTERM	P	
N18	VccDFTERM	P	
AF15	VccPLLEXPU	P	
AH20	VccPLLSAS0	P	
AJ20	VccPLLSAS0	P	
AF23	VccPLLSAS1	P	
L28	vccRTC	P	
AF22	VccSAS1_5	P	
AH22	VccSAS1_5	P	
AJ22	VccSAS1_5	P	
AC22	VccSCUS	P	
AC23	VccSCUS	P	
AC24	VccSCUS	P	
AD22	VccSCUS	P	
AD23	VccSCUS	P	
AD24	VccSCUS	P	
N25	vccSPI	P	
R25	vccsus3_3	P	
T15	vccsus3_3	P	
T25	vccsus3_3	P	
W25	vccsus3_3	P	
W26	vccsus3_3	P	
W28	vccsus3_3	P	
U25	VccSusHDA	P	
AC15	VCCXUS	P	
AD15	VCCXUS	P	
AE12	VCCXUS	P	
A10	VSS	G	
A11	VSS	G	
A13	VSS	G	
A16	VSS	G	
A19	VSS	G	
A21	VSS	G	
A24	VSS	G	
A26	VSS	G	
A29	VSS	G	
A3	VSS	G	
A31	VSS	G	
A36	VSS	G	
A4	VSS	G	
A6	VSS	G	
A8	VSS	G	
AA1	VSS	G	
AA3	VSS	G	
AA33	VSS	G	
AA37	VSS	G	
AA39	VSS	G	
AB11	VSS	G	
AB15	VSS	G	
AB16	VSS	G	
AB17	VSS	G	
AB18	VSS	G	
AB19	VSS	G	
AB20	VSS	G	
AB22	VSS	G	
AB23	VSS	G	
AB24	VSS	G	
AB25	VSS	G	
AB26	VSS	G	
AB28	VSS	G	
AB7	VSS	G	
AC11	VSS	G	
AC33	VSS	G	
AC7	VSS	G	
AD1	VSS	G	
AD3	VSS	G	
AD30	VSS	G	
AD33	VSS	G	
AD37	VSS	G	
AD39	VSS	G	
AE10	VSS	G	
AE15	VSS	G	
AE16	VSS	G	
AE17	VSS	G	
AE18	VSS	G	
AE19	VSS	G	
AE20	VSS	G	
AE22	VSS	G	
AE23	VSS	G	
AE25	VSS	G	
AE26	VSS	G	
AE28	VSS	G	
AE6	VSS	G	
AF1	VSS	G	
AF10	VSS	G	
AF18	VSS	G	
AF19	VSS	G	
AF3	VSS	G	
AF33	VSS	G	
AF37	VSS	G	
AF39	VSS	G	
AF6	VSS	G	
AG33	VSS	G	
AH11	VSS	G	
AH17	VSS	G	
AH19	VSS	G	
AH24	VSS	G	
AH7	VSS	G	
AJ1	VSS	G	
AJ11	VSS	G	
AJ17	VSS	G	
AJ19	VSS	G	
AJ24	VSS	G	
AJ29	VSS	G	
AJ3	VSS	G	
AJ33	VSS	G	
AJ37	VSS	G	
AJ39	VSS	G	
AJ7	VSS	G	
AL1	VSS	G	
AL10	VSS	G	
AL3	VSS	G	
AL37	VSS	G	
AL39	VSS	G	
AL6	VSS	G	
AM10	VSS	G	
AM15	VSS	G	
AM16	VSS	G	
AM21	VSS	G	
AM22	VSS	G	
AM27	VSS	G	
AM28	VSS	G	
AM33	VSS	G	
AM34	VSS	G	
AM4	VSS	G	
AM9	VSS	G	
AN12	VSS	G	
AN13	VSS	G	
AN18	VSS	G	
AN19	VSS	G	
AN24	VSS	G	
AN25	VSS	G	
AN30	VSS	G	
AN31	VSS	G	
AN36	VSS	G	
AN6	VSS	G	
AN7	VSS	G	
AP37	VSS	G	
AP39	VSS	G	
AR3	VSS	G	
AU11	VSS	G	
AU13	VSS	G	
AU16	VSS	G	
AU19	VSS	G	
AU21	VSS	G	
AU24	VSS	G	
AU26	VSS	G	
AU29	VSS	G	
AU31	VSS	G	
AU34	VSS	G	
AU6	VSS	G	
AU8	VSS	G	
AW11	VSS	G	
AW13	VSS	G	
AW16	VSS	G	
AW19	VSS	G	
AW21	VSS	G	
AW24	VSS	G	
AW26	VSS	G	
AW29	VSS	G	
AW3	VSS	G	
AW31	VSS	G	
AW34	VSS	G	
AW36	VSS	G	
AW37	VSS	G	
AW4	VSS	G	
AW6	VSS	G	
AW8	VSS	G	
B9	VSS	G	
C1	VSS	G	
C11	VSS	G	
C13	VSS	G	
C16	VSS	G	
C19	VSS	G	
C21	VSS	G	
C24	VSS	G	
C26	VSS	G	
C29	VSS	G	
C34	VSS	G	
C6	VSS	G	
C8	VSS	G	
D1	VSS	G	
D39	VSS	G	
F1	VSS	G	
F3	VSS	G	
F37	VSS	G	
G10	VSS	G	
G12	VSS	G	
G13	VSS	G	
G15	VSS	G	
G16	VSS	G	
G18	VSS	G	
G19	VSS	G	
G21	VSS	G	
G22	VSS	G	
G24	VSS	G	
G25	VSS	G	
G27	VSS	G	
G28	VSS	G	
G30	VSS	G	
G31	VSS	G	
G33	VSS	G	
G34	VSS	G	
G4	VSS	G	
G6	VSS	G	
G7	VSS	G	
G9	VSS	G	
H1	VSS	G	
H3	VSS	G	
H39	VSS	G	
L1	VSS	G	
L11	VSS	G	
L22	VSS	G	
L3	VSS	G	
L37	VSS	G	
L7	VSS	G	
M15	VSS	G	
M16	VSS	G	
M17	VSS	G	
M22	VSS	G	
M23	VSS	G	
M26	VSS	G	
M29	VSS	G	
M3	VSS	G	
M33	VSS	G	
N1	VSS	G	
N10	VSS	G	
N19	VSS	G	
N2	VSS	G	
N3	VSS	G	
N37	VSS	G	
N39	VSS	G	
N6	VSS	G	
P10	VSS	G	
P30	VSS	G	
P33	VSS	G	
P6	VSS	G	
R15	VSS	G	
R16	VSS	G	
R17	VSS	G	
R18	VSS	G	
R19	VSS	G	
R20	VSS	G	
R23	VSS	G	
R24	VSS	G	
R26	VSS	G	
R28	VSS	G	
R30	VSS	G	
R33	VSS	G	
T1	VSS	G	
T11	VSS	G	
T3	VSS	G	
T37	VSS	G	
T39	VSS	G	
T7	VSS	G	
T9	VSS	G	
U11	VSS	G	
U30	VSS	G	
U33	VSS	G	
U7	VSS	G	
V15	VSS	G	
V16	VSS	G	
V17	VSS	G	
V18	VSS	G	
V19	VSS	G	
V20	VSS	G	
V22	VSS	G	
V23	VSS	G	
V25	VSS	G	
V26	VSS	G	
V28	VSS	G	
V33	VSS	G	
W1	VSS	G	
W10	VSS	G	
W3	VSS	G	
W37	VSS	G	
W39	VSS	G	
W6	VSS	G	
W8	VSS	G	
W9	VSS	G	
Y10	VSS	G	
Y33	VSS	G	
Y6	VSS	G	
J36	WAKE#	I	

		
		
begin power_up_sequence		
   #RSMRSTB is a hard reset to indicate the suswell is valid		
   #DPWROK is a hard reset to indicate the dswwell is valid		
   #RTCRSTB is a hard reset to indicate the rtcwell is valid 		
   #APWROK is a hard reset to indicate the mewell is valid		
   #PCH_PWROK is a hard reset to indicate the corewell is valid 		
   #SYS_PWROK is a hard reset to indicate the system has been power up		
   #SRTCRSTB is a hard strap to enable bscan		
   #INTVRMEN and DSWOVRMEN is are the non reset pins that incorporated with power up signals.		
   #INTVRMEN and DSWOVRMEN connect to Vss to disable VRM and connect to VccRTC power plane to enable VRM.
   # User can drive INTVRMEN and DSWOVRMEN to Vss or Vcc to suit the board design throughout entire boundary scan testing.		


   dl(RSMRSTB, DPWROK, PCH_PWROK, APWROK, SYS_PWROK,  INTVRMEN, DSWVRMEN) dh(SRTCRSTB, RTCRSTB);

   loop 10u #hold srtcrstb drive high for 10us
     dh(SRTCRSTB, RTCRSTB);
   end loop

   loop 2u 
     dl(SRTCRSTB, RTCRSTB);
   end loop

   loop 10u 
     dh(RSMRSTB, DPWROK);
   end loop

   loop 20u 
     dh(SRTCRSTB, RTCRSTB, PCH_PWROK, APWROK, SYS_PWROK);
   end loop

   hold(RSMRSTB, DPWROK, RTCRSTB, PCH_PWROK, APWROK, INTVRMEN, DSWOVRMEN)
end
