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Intel’s new server chipsets for the Intel® Xeon® processor 5000 series enable Intel® dual-processor (DP) balanced server platforms that are efficient, dependable, and responsive.
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Product information
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Description
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Intel® dual-core processor-based platforms help businesses better utilize assets with effective virtualization and increase density in their data centers through optimized power and thermal features.
With the Intel 5000P or Intel 5000V chipset and Intel Xeon processor 5000 series, system designers can offer new platforms that help IT services move ahead with increased productivity,higher throughput, and faster time-to-solution.
The Intel® 5000P chipset, the next generation Intel® dual-processor (DP) server chipset technology, offers increased graphics performance, reduced power consumption, and improved platform reliability and system manageability.
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Features and Benefits
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Supports two Intel® Xeon® processors 5000Δ series
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Optimized performance for intensive computing demands of enterprise and small to medium business servers, plus high performance computing (HPC) applications. |
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1066 / 1333
1
MHz dual independent buses
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Increased bus bandwidth of up to 3X over 800 MHz based systems. |
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FB DIMM 533/667 MHz memory interface
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Offers a maximum memory bandwidth up to 17 GB/s for 533 MHz and 21 GB/s for 667 MHz.
Increased dual in-line memory modules (DIMMs) per system, providing enhanced memory scalability for memory-intensive applications.
Up to 64 GB memory capacity.
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PCI Express*
2
I/O
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Serial I/O technology provides a direct connection between the MCH and PCI Express components/adapters, with bandwidth up to 4 GB/s on each PCI Express x8 interface. |
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Intel® 6700PXH 64-bit PCI Hub
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Optional component introduces next-generation PCI/PCI-X performance and significant enhancements to platform flexibility.
Supports two independent 64-bit, 133 MHz PCI-X segments and two Hot-Plug controllers (one per segment).
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Advanced platform remote access service (RAS)
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Features such as memory Error Correction Code (ECC), Intel® x4 Single Device Data Correction (x4 SDDC)3, DIMM sparing and DIMM scrubbing for improved system reliability.
The System Management Bus (SMBus) port hooks into the Intel® 5000P MCH chipset for remote management operation and support for a variety of third-party base management controller (BMC) and BIOS solutions.
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Intel® Hub Interface 1.5 connection to the MCH chipset
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Point-to-point connection between the MCH chipset and the Intel® 82801ER I/O Controller Hub or Intel® 6300ESB I/O Controller Hub devices provides as much as 266 MB/s of bandwidth. |
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Packaging information
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Intel® chipsets may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are available on request.
Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See page for details.
1 The 1333 MHz system bus feature will be available in the second half of 2006.
2 PCI Express* reduced power-state "L0s" is not supported. 3 In an x4 DDR memory device, the Intel® x4 Single Device Data Correction (x4 SDDC) provides error detection and correction for 1, 2, 3 or 4 data bits within that single device and provides error detection, up to 8 data bits, within two devices. For more information on performance tests and on the performance of Intel® products, visit page.
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