Intel® QuickAssist Technology

Intel is committed to providing open platforms for innovation—and the market for specialized accelerators is no exception. The Intel® QuickAssist Technology initiative represents a comprehensive visionary approach for supporting accelerators on Intel technology.
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Intel QuickAssist Technology Accelerator Abstraction Layer (AAL) › (PDF 246KB)

The need for increasing performance on tasks like medical imaging, financial modeling and cryptography has led to the development of accelerators requiring high bandwidth and low latency. Under the banner of the Intel® QuickAssist Technology, Intel is providing strategic support for accelerators through several major initiatives: open accelerator attach strategy encompassing industry solutions; Intel QuickAssist Technology enabled Front Side Bus Field Programmable Gate Array (FSB-FPGA) hardware modules; the Intel® QuickAssist Technology Accelerator Abstraction Layer (AAL); and Tolapai, an integrated System on a Chip (SOC) accelerator taking advantage of Intel QuickAssist Architecture.

Additionally, Intel is working with IBM and the PCI-SIG on Geneseo, a series of improvements to PCI Express* technology.

Intel will continue to take an open approach to tightly-coupled in-socket accelerators, providing not only the physical ability to connect to the FSB but also working with the leading FPGA manufacturers to provide the register transfer logic (RTL) and drivers necessary to create fully optimized FSB-attached solutions.

Intel AAL will promote innovation in tightly-coupled FSB accelerators by removing the need for ISVs to develop proprietary acceleration layers for each new device. This will also have the effect of freeing end users of being tied to a particular type of accelerator and maintain agility by choosing the devices and solutions that are right for them in the face of ever-changing market conditions. AAL will be built to provide common protocols for communicating data and instructions to and from FSB-FPGA accelerators, as well as common policies for managing memory and dealing with exceptions. AAL provides services such as discovery, registration and binding of accelerator functions across hardware and software environments.

AAL will be optimized for parallel processing and will allow an accelerator to be shared among multiple applications (assuming the accelerator allows it). AAL is thread and multi-core safe and built to last through future generations of multi-core and multi-thread processor designs.

Developers will be able use the programming languages and environments they already know, as AAL will be compatible with most of them, and they will also find that it can support a wide variety of hardware-based acceleration strategies. AAL will be released in versions for all significant operating systems, allowing it to be implemented in the widest variety of settings. Intel is committed to working with hardware vendors who build FSB-attached accelerator modules, as well providers of compilers for FPGAs, to integrate AAL into their offerings.

A new product is coming in 2008, codenamed Tolapai, that will expand the solution space of Small Form Factor (SFF) accelerators. Tolapai is an integrated SOC (system-on-a-chip), combining an Intel Architecture (IA) core, memory controller and I/O controller into a single chip, combined with Intel QuickAssist Integrated Accelerator Technology. This solution will support a range of applications including communications and security processing while remaining cost-effective and power-efficient.

Because a large majority of accelerators on the market today attach via PCI Express (PCIe), Intel and IBM are proposing a series of significant improvements to the PCIe framework that will encourage innovation across markets, systems and functions. These improvements are gathered together under the codename Geneseo.

The proposed Geneseo improvements include:

Improved bandwidth efficiency        Faster link acquisition        Efficient & reduced latency accesses        Reduced synchronization overhead        "Loose" transaction ordering        Dynamic power/thermal control        Streamlined software model        Improved bandwidth