Intel has reached a significant milestone in developing next-generation chip manufacturing technology by building fully functional 70-megabit static random access memory (SRAM) chips with more than half a billion transistors. The new chips were manufactured using the world's most advanced 65-nanometer (nm) process technology. The achievement extends Intel's efforts to develop new manufacturing process technology every two years, in accordance with Moore's Law.

The transistors in the new 65-nm (a nanometer is one-billionth of a meter) technology have gates (the switch that turns a transistor on and off) measuring 35 nm, approximately 30 percent smaller than the gate lengths on the earlier 90-nm technology. About 100 of these gates could fit inside the diameter of a human red blood cell.

The new process technology increases the number of tiny transistors squeezed onto a single chip, providing the foundation on which to deliver future multicore processors. It will also enable Intel to design innovative features into future products, including virtualization and security capabilities. This new 65-nm process technology also includes several unique power-saving and performance-enhancing features.

"Intel continues to meet the increasing challenges of scaling by innovating with new materials, processes and device structures," said Sunlin Chou, senior vice president and general manager of Intel's Technology and Manufacturing Group. "Intel's 65-nm process technology has industry-leading density, performance and power reduction features that will enable future chips with increased capabilities and performance. Intel's 65-nm technology is on track for delivery in 2005 to extend the benefits of Moore's Law."

In November 2003, Intel used 65-nm process to build 4-megabit SRAMs, and has since then fabricated fully functional 70-megabit SRAMs on this process with a very small die area of 110 mm² (see photo above). Small SRAM cells allow for the integration of larger caches in processors, increasing performance. Each SRAM memory cell has six transistors packed into an area of 0.57 µm² (see photo below). Some 10 million of these transistors could fit in one square millimeter, roughly the size of the tip of a ball point pen.

According to Moore's Law, the number of transistors on a chip roughly doubles every two years, resulting in more features, increased performance, and decreased cost per transistor. As transistors get smaller, more power and heat dissipation issues develop. As a result, implementing new features, techniques and structures is imperative to continuing this progress. Intel has addressed these challenges by integrating power-saving features into the 65-nm process technology. These features are critical to delivering power-efficient computing and communications products in the future.

Intel's leading strained silicon technology, first implemented in our 90-nm process technology, is further enhanced in the 65-nm technology. The second generation of Intel strained silicon increases transistor performance by 10 to 15 percent without increasing leakage. Conversely, these transistors can cut leakage by four times at constant performance compared to 90-nm transistors. As a result, the transistors on Intel's 65-nm process have improved performance without significant increases in leakage (greater electrical current leakage results in greater heat generation).

Intel's 65-nm transistors have a reduced gate length of 35 nm and a gate oxide thickness of 1.2 nm, which combine to provide improved performance and reduced gate capacitance. The reduced gate capacitance ultimately lowers a chip's active power. The new process also integrates eight copper interconnect layers (see photo) and uses a "low-k" dielectric material that increases the signal speed inside the chip and reduces chip power consumption.

"Sleep transistors" have also been implemented in the 65-nm SRAM. Sleep transistors shut off the current flow to large blocks of the SRAM when they are not being utilized, eliminating a significant source of power consumption on a chip. This feature is especially beneficial for battery-powered devices, like laptops.

"Intel has been actively working on the power and heat dissipation challenges faced by the semiconductor industry," Chou said. "We have taken a holistic approach by developing solutions that involve systems, chips and technologies, and include innovations on our 65-nm technology that go beyond simply extending prior techniques."

Select from the following resources and delve into the history, applications, and future of Moore's Law.

• Intel Silicon Innovation: Fueling New Solutions for the Digital Planet [PDF 909KB]
• Cramming More Components Onto Integrated Circuits [PDF 167KB] Gordon E. Moore, Electronics, April 19, 1965
• No Exponential is Forever...but We Can Delay 'Forever' [PDF 2MB]
  Gordon E. Moore, presentation at International Solid State Circuits Conference (ISSCC), February 10, 2003
• Moore Optimistic on Moore's Law
• Gordon E. Moore Biography