The IXP compiler (auto-partitioning mode) targets to relieve the programmer’s efforts of developing network applications for IXP, the Internet exchange Processor. Since IXP is an advanced architecture that contains Multi-MicroEngine and Multi-Threading features, it may be hard for programmers to write high performance network packet processing applications without knowing the architecture details. Our compiler makes the program mode much easier by providing the capability of automatic program partition and automatic threading partition, i.e., the compiler can decide which code portion run on which MicroEngine in which kind of threading mode although the input program has sequential semantics, as indicated in the following figure. In short, our compiler brings our customers the value of easy-of-programming, full modularity, high code reuse rate, short development cycles and good performance.

The Intel Itanium processor family has been architected to provide industry-leading performance and capabilities on high-end applications. While optimal performance is realized using native applications, support for IA-32 applications is also provided to enable customers’ flexibility and protect their investment on software in migrating to Itanium 2-based Solutions.

Current Itanium 2 processors have provided the capability to support IA-32 applications using on-die hardware. To enhance this support and add flexibility, Intel developed a new technology called the IA-32 Execution Layer (IA-32 EL) that is designed to replace the on-die hardware in future Itanium 2 processors.

IA-32 EL is a software that will ship with Itanium-based operating systems and will convert IA-32 instructions into Itanium instructions via dynamic translation.

IA-32 EL enhances Itanium 2 processor support for IA-32 applications with the following benefits:

ICSC IA-32 Execution Layer team is composed of 11 software engineers. Since established in Feb 2000, the team has successfully released three version of IA-32 EL product. In addition, the team has four papers accepted by international conference and twenty patents filed to USPTO (United State Patent and Trademark Office).

J2ME team is focus on building the whole Java ME stack to enrich and standardize the Java runtime environment for handheld device such as mobile phone, PDA etc.. As an industry leader on semi-conductor, Intel has invested on research, development, manufacture and platform distribution to customer and end users for more than 5 years. We found there are big diversities on the SW solutions, each OEM has its own stack solution. Along with the rapid growing of the mobile phone market, Java ME technology is playing more and more important role in handheld device to standardize the SW solution which could greatly decrease the workload of application developers and bring marvelous convenience to end users. 

Java Virtual Machine (Standard Version) is the base of running enterprise Java applications. The goal of our team is to make enterprise Java application run optimally on Intel Server Platforms by optimizing JVM. By deep understanding of Intel server platform architecture and J2SE/J2EE service stack, we developed and applied a series of optimization technologies to JIT, Garbage Collection and JNI components which greatly improved the performance of enterprise Java application. Our job makes the optimized JVM an industry leader in many stand performance benchmark tests. 

Retargetable Compiler Technology (RCT) is designed to easily support different backend. Currently it supports three backend: IXP, MSA and IA32.

RCT team works on improving the infrastructure of RCT, which helps to provide better service for IXP and MSA compiler. Currently, the team focuses on reducing compile time and improving debugbility of IXP and MSA compiler for optimized code. Then improve usability of the compilers.

The team develops automatic quantitive debugbility measurement tools, which automatically measure the impact on debug information of optimization and give a quantitive report. With these tools, it is easy to check which optimization loses the debug information.

Microengines are 32-bit programmable high performance RISC engines on Intel® Internet Exchange Architecture (IXA) network processor that provides support for software-controlled multi-threaded operations to do most of the programmable pre-packet processing in the network processor.

Microengine Tools (ME-Tools) is the core component of the Intel® IXA Software Development Kit (SDK), which provided Microengine development chain of tools, such as Assembler, Linker, Loader, Debugger, Simulator, etc. It also provides the Developer Workbench an integrated development environment including all tools above, which provide advanced graphical cycle-accurate simulation, profiling, and debugging. It enables faster prototyping, intuitive optimization, and fast time-to-market development of networking applications for the highly parallel, multi-threaded, MEv2 architecture.

The Microengine Tools supports developing and debugging applications running on Wind River VxWorks 5.5.1 and MontaVista Linux Professional Edition* 3.1 embedded operating systems.

ME-Tools team is working on provide tools support to next generation Intel® IXA network processor and communication processor.

Intel® Micro Signal Architecture (Intel® MSA) incorporates Digital Signal Processor (DSP) and microcontroller features in a single platform. It combines a 32-bit RISC instruction set, dual 16-bit multiply accumulate (MAC) units, 8-bit video processing instructions and SIMD multi-media functionalities; it also incorporates Dynamic Power Management (DPM) capabilities and results in optimized power consumption and performance for real-time applications. It will be widely used in handhold devices and set top boxes etc. Based on Intel® MSA and Intel XScale® architecture, the Intel PXA9xx cellular processor, has been adopted by Research In Motion (RIM) in their first EDGE (Enhanced Data Rates for Global Evolution) enabled BlackBerry® 8700 series. And RIM will continue to use Intel communications technology in future BlackBerry® devices.

Intel® Micro Signal Architecture SDK (Intel® MSA SDK) includes Compiler, C/C++ Library, Assembler, Linker, Profiler, Simulator and Debugger etc. The Intel MSA Compiler generated code has smaller code size and higher runtime performance, and it also supports debugging for optimized code; the Intel MSA Tool chain also supports Overlay technology and unreferenced function and data elimination; all of these ease and speed engineer’s developing and debugging work on Intel® MSA applications.

ICSC MSA Compiler & Tools team is working on further improving performance of Intel MSA Compiler and developing graphic expert Linker etc. in order to provide user higher quality and more user friendly Intel® MSA SDK.

The XML Core Processing Project supplies high performance XML libraries that conform to industry standard like JAXP or other “de facto” industry standard. With accelerated XML processing & security, The XML libraries can be used in various functionality such as wire-speed software XML acceleration, XML format transformation, gateway security, streaming, and routing.

The XML Libraries are powered by the patent-pending XML EventStream Operating System™ (XESOS™), pronounced “ZEE SOS”. XESOS™ is a hardware independent technology that utilizes a specialized data stream called the XML EventStream to provide a highly optimized pipeline-processing model for XML processing & security. EventStream is a highly efficient and flexible representation of an input XML document. XESOS™ includes highly efficient components for parsing, schema validation, streaming, XSLT transformation, XPath processing and XML Security, all of which are custom-built for performance and standards-compliance.

Built from the ground up for performance, security & flexibility, XESOS™ is based on an ideal blend of event-based and multi-threaded architectures. XESOS™ is a highly stable, extensible, and comprehensive XML processing engine that is the most flexible product platform on the market today. As a result, the XML libraries can provide sustained high performance in the face of varying XML document sizes and external dependencies.