Faculty Profile

University

Weseda University

Focus Area

Manufacturing

Curriculum Development
Research
Industry-Higher Education Relations

Background

Graduated from Waseda University in 1972 (M.E.)
Joined Fujitsu Laboratories Ltd. in 1972 (-1996)
Engaged on optical devices for fiber telecomminications
Received 9th K.Sakurai Memorial Award from OITDA in 1993
Moved to Waseda Univ as a professor of applied physics in 1996
Fellow of the Japan Society of Applied Physics in 2008
Steering Chair of "Microoptics Group" under OSJ/JSAP(2001-  )
Director of Research Promotion, Waseda Univ. (2006-  )

Research Interest

Photonics

Research Publications

H. Nakajima , "LiNbO3 Based Optical Devices: Evolution and Future Prospect," (Plenary) , 14th Microoptics Conference (MOC’08), 2008.9 (Brussels)

A. Kobayashi, H. Okayama and H. Nakajima ,"Microsphere/Cylinder Wavwguide Resonator for Direct Light BeamCoupling Using Metalic Core and High Reflactive Index Shell," Japan. J. Appl. Phys. 47 , pp.6750-6753 (2008)

H. Nakajima ,"Welcome to Microoptics World" ( Tutorial ) , TU 0, 13th Microoptics Conference (MOC’07), 2007.10 (Takamatsu)

S. Kogahara, S. Shinada, S. Nakajima, T. Kawanishi, H. Nakajima and M. Izutsu, "Reciprocating Optical Modulation on Erbium-Doped LiNbO3 for Harmonic Generation," IEEE PTL. 19 , 1565-1567 (2007)

Y. Naoi, H. Okayama and H. Nakajima , "Sensor for refractive index variation of an optical surface using a high-reflractive-index waveguide," Opt. Eng. 46 , 104601 (2007)

S. Kurimura, Y. Kato, M. Maruyama, Y. Usui, and H. Nakajima , "Quasi-phase-matched adhered ridge waveguide in LiNbO3," Appl. Phys. Lett., 89 , 191123 (2006.11)

M. Maruyama, H. Nakajima , S. Kurimura, N.-E. Yu, and K. Kitamura, "70-mm-long periodically poled Mg-doped stoichiometric LiNbO3 devices for nanosecond optical parametric generation," Appl. Phys. Lett., 89 , 011101 (2006.7)
 
H.Nakajima , "Development on Guided-Wave Switch Arrays (Invited Paper) ," IEICE TRANS. ELECTRON., E82-C , 297-304 (1999).

H.Nakajima , "Temperature-stable, low-loss Ti:LiNbO3 devices (Invited) ," IOOC'89, 19D4-2, 172-173, Kobe (1989).

I.Sawaki, T.Shimoe, H.Nakamoto, T.Iwama, T.Yamane, and H.Nakajima , "Rectangularly configured 4x4 Ti:LiNbO3 matrix switch with low drive voltage," IEEE J. Selected Areas in Comm., 6 , 1267-1272 (1988).

Website

http://www.pic.phys.waseda.ac.jp/

University

Waseda University

Focus Area

Manufacturing
Systems & Architecture
Software for Multicore

Background

B.S.(1980,Waseda), M.S.(1982,Waseda)

Dr. Eng. (1985,Waseda). Res. Assoc.(1983,Waseda)

Assist. Prof.(1986. Waseda), Assoc. Prof.(1988,Waseda)

Prof.(1997, Waseda).

Visiting Scholar (1985. Univ. California at Berkeley)

Visiting Research Scholar(1989-1990. Center for Supercomputing R & D, Univ. of Illinois at Urbana-Champaign)

Young Author Prize: IFAC Triennial World Congress(1987)

IPSJ Sakai Memorial Special Award (1997)

STARC (Semiconductor Technology Academic Research Center) Industry-Academia Cooperative Research Award (2005)
2008 LSI of The Year The Second Prize (2008)

Prof. Kasahara led several Japanese national projects, such as Millennium Project IT21 METI/NEDO "Advanced Parallelizing Compiler", METI/NEDO "Multi-core for Real-time Consumer Electronics" and "Advanced Heterogeneous Multiprocessor".

He has served as a chair of IEEE Computer Society Japan Chapter, a Board member of IEEE Tokyo Section, a member of IEEE Japan Council Long Range Strategy Committee, a chair of the IPSJ special interest group on Computer Architecture, Chairs of Hardware Editorial Board of the Journal and Magazine of IPSJ and program committees of 50 international conferences on Super computing and Parallel Processing including a Vice Program Chair of ENIAC50th Anniversary ACM International Conference on Supercomputing 1996.

Also, Dr. Kasahara was a member of the Earth Simulator Advisory Committee.

Research Interest

Multicores, Parallelizing Compilers, Low Power

Research Publications

"Heterogeneous Multi-core Architecture that Enables 54x AAC-LC Stereo Encoding", IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp.902-910, Apr. 2008.

"An 8640 MIPS SoC with Independent Power-off Control of 8 CPU and 8 RAMS by an Automatic Parallelizing Compiler", Proc. of International Solid State Circuits Conference (ISSCC2008), Feb. 2008.

"Compiler Control Power Saving Scheme for Multi Core Processors", Proc. of The 18th International Workshop on Languages and Compilers for Parallel Computing (LCPC2005), Oct. 2005.

"A Data-Localization Compilation Scheme Using Partial Static Task Assignment for Fortran Coarse Grain Parallel Processing", Journal of Parallel Computing, Special Issue on Languages and Compilers for parallel Computers, pp.579-596, May. 1998.

"Data-Localization for Fortran Macro-Dataflow Computation Using Partial Static Task Assignment", Proc. of 10th ACM International Conference on Supercomputing, pp.61-68, May. 1996.

"A Multi-grain Parallelizing Compilation Scheme for OSCAR (Optimally Scheduled Advanced Multiprocessor)", Fourth International Workshop on Languages and Compilers for Parallel Computing, pp.283-297, Aug. 1991.

"Parallel Processing of Near Fine Grain Tasks Using Static Scheduling on OSCAR (Optimally Scheduled Advanced Multiprocessor)", Proceedings of IEEE Supercomputing '90, pp.856-864, Nov. 1990.

"Parallel Processing of Robot Arm Control Computation on a Multimicroprocessor System", IEEE Journal of Robotics and Automation, Vol. RA-1, No. 2, Jun. 1985.

"An Approach to Supercomputing Using Multiprocessor Scheduling Algorithms", Proc. of IEEE 1st International Conf. on Supercomputing, Dec. 1985.

Website

http://www.kasahara.cs.waseda.ac.jp

University

Tokyo Institute of Technology

Focus Area

Manufacturing
Systems & Architecture
Software for Multicore

Background

B.E., M.E. and Ph.D. degrees in Electronics Engineering from Tokyo Institute of Technology, Tokyo, Japan, in 1977, 1979 and 1982,

From 1982-2000, RIEC, Tohoku University, Sendai, Japan since 1982.  From 2000, a Professor, Tokyo Institute of Technology, Yokohama, Japan.

He is a distinguished lecturer of Electron Device Society, IEEE from 2001. He is also a Project Leader of Dream Chip Project, NEDO, from 2008.

Research Interest

Interconnect design, RF CMOS circuit,  RF MEMS, in vivo communication

Research Publications

H. Ito, M. Kimura, K. Miyashita, T. Ishii, K. Okada, K. Masu, "A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications," IEEE JSSCC, 43(4) 1020 (2008).

K. Masu, K. Okada, "Reconfigurable RF CMOS Circuit for Cognitive Radio (Invited Paper)", IEICE, E91-B(1), 10 (2008)

K. Masu, K. Okada, and H. Ito, "RF Passive Components Using Metal Line on Si CMOS" (Invited Paper), IEICE, E89-C(6), 681 (2006.

H. Ito, K. Masu, "A Simple Through-Only De-Embedding Method for On-Wafer S-Parameter Measurements up to 110 GHz", IEEE MTT-S IMS 2008,Atlanta, 383 (2008).

K. Ohashi, Y. Kobayashi, H. Ito, K. Okada, H. Hatakeyama, T. Aizawa, T. Ito, R. Yamauchi, K. Masu, "A Low Phase Noise LC-VCO with a High-Q Inductor Fabricated by Wafer Level Package Technology", IEEE RFIC2008, Atlanta, 123 (2008)

Y. Kobayashi, K. Ohashi, Yusaku Ito, H. Ito, K. Okada, and K. Masu, "A 0.49-6.50GHz Wideband LC-VCO with High-IRR in a 180 nm CMOS Technology," Int. Conf. on SSDM, Tukuba, 268 (2007)

T. Sato, S. Hagiwara, T. Uezono, and K. Masu, "Weakness identification for effective repair of power distribution network", 17th PATMOS, Göteborg, Sweden, 222 (2007)

H. Ito, M. Kimura, K. Okada, and K. Masu, "A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers," Symp. VLSI Circuits, Kyoto, 136 (2007)

H. Ito, J. Seita, T. Ishii, H. Sugita, K. Okada, and K. Masu, "A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for a RC Interconnect Alternative," IEEE IITC, San Francisco, 193 (2007).

S. Amakawa, Takumi Uezono, Takashi Sato, K. Okada, and K. Masu, "Adaptable wire-length distribution with tunable occupation probability," Int. Workshop on System Level Interconnect Prediction (SLIP), Austin, 1 (2007)

Email address

masu@ieee.org

University

Tokyo Institute of Technology

Focus Area

Manufacturing

Background

Education:

• Ph.D. in Department of Communications and Computer Engineering, Graduate school of Informatics, Kyoto University, Japan, March 2003
• M.E. in Department of Communications and Computer Engineering, Graduate school of Informatics, Kyoto University, Japan, March 2000
• B.E. in School of Electronic Engineering, Kyoto University, Japan, March 1998

Job:

• Associate Professor, Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology, April 2007-(with Prof. Akira Matsuzawa)
• Assistant Professor, Integrated Research Institute, Tokyo Institute of Technology, Oct. 2005 - Mar. 2007
• Assistant Professor, Precision and Intelligence Laboratory, Tokyo Institute of Technology, April 2003 - Sept. 2005 - (with Prof. Kazuya Masu)

Research Interest

Analog/RF circuit design

Research Publications

K. Okada, H. Sugawara, H. Ito, K. Itoi, M. Sato, H. Abe, T. Ito, and K. Masu, "On-Chip High-Q Variable Inductor Using Wafer-Level Chip-Scale Package Technology," IEEE Transactions on Electron Devices, Sep. 2006.

T. Yammouch, K. Okada, and K. Masu, "Physical Modeling of MEMS Variable Inductor," IEEE Transactions on Circuits and Systems II, May 2008.

H. Ito, M. Kimura, K. Miyashita, T. Ishii, K. Okada, and K. Masu, "A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications," IEEE Journal of Solid-State Circuits, April 2008.

W. Chaivipas, K. Okada, and A. Matsuzawa, "A 80GHz Voltage Controlled Oscillator With a Negative Varactor in 90nm CMOS Technology," IEEE A-SSCC 2008.

K. Ohashi, Y. Kobayashi, H. Ito, K. Okada, H. Hatakeyama, T. Aizawa, T. Ito, R. Yamauchi, and K. Masu, "A Low Phase Noise LC-VCO with a High-Q Inductor Fabricated by Wafer Level Package Technology," IEEE RFIC 2008.

Y. Ito, H. Sugawara, K. Okada, and K. Masu, "A 0.98 to 6.6GHz Tunable Wideband VCO in a 180nm CMOS Technology for Reconfigurable Radio Transceiver," IEEE A-SSCC 2006.

T. Ito, D. Kawazoe, K. Okada, and K. Masu, "A DC-7GHz Small-Area Distributed Amplifier Using 5-port Inductors in a 180nm Si CMOS Technology," IEEE A-SSCC 2006.

H. Ito, M. Kimura, K. Okada, and K. Masu, "A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers," IEEE Symposium on VLSI Circuits 2007.

H. Ito, J. Inoue, S. Gomi, H. Sugita, K. Okada, and K. Masu, "On-Chip Transmission Line for Long Global Interconnects," IEEE IEDM 2004

K. Okada, K. Yamaoka, and H. Onodera, "A Statistical Gate-Delay Model Considering Intra-Gate Variability," IEEE/ACM ICCAD 2003.

Website

http://www.ssc.pe.titech.ac.jp/~okada/index-e.html

University

The University of Tokyo

Focus Area

MOT & Global Collaborative research Development

Background

Became Professor, The University of Tokyo in 2005, and prior to that he had been working with several US high-tech companies for more than 20 years as GM of Japan subsidiaries and was responsible for whole operation of subsidiary including sales, marketing, technical support as well as administrative works. All of them are in their start-up phases of operation to expand the business in the competitive market of Japan.

Prior to that he had been working with Mitsubishi Heavy Industries for 15 years on the design and construction of nuclear power plants as nuclear engineer and project manager.

Research Interest

ICT and Nano-Technology

Research Publications

None

Website

http://www.ducr.u-tokyo.ac.jp/en/

University

Kobe University

Focus Area

Systems & Architecture

Background

He received M.S. degree in electronic engineering and Ph.D. degrees in Electrical Engineering from Nagoya University, Nagoya, Japan in 1977 and  in 1998, respectively.  He joined the LSI Laboratory, Mitsubishi Electric Power Products Inc., Itami, Japan, in April 1977. During 1978-1983 he was engaged in the design of NMOS and CMOS static RAM. From 1984, he was involved in research and development of multimedia ULSI systems for digital broadcasting and digital communication systems based on MPEG2 and MPEG4 Codec LSI core technology. Since 2004, he has been a professor of Dept. of Computer and Systems Engineering in Kobe University, Japan. His current activity is focused on the research and development of multimedia and ubiquitous media VLSI systems including an ultra low power image compression processor and a low power wireless interface circuit. He received the R&D100 awards from the R&D magazine for the development of the DISP and the development of the realtime MPEG2 video encoder chipset in 1990 and 1996, respectively.

Research Interest

VLSI Circuit and Systems

Research Publications

"A sub 100 mW H.264 MP@L4.1 Integer-pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-connected Systolic Array and Segmentation-free, Rectangle-access Search-window Buffer,"

"A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition,"

"Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme,"
 
"A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond,"

"A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline,"

"A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High Resolution Video Application",

"A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation,"

"A Single Chip H.32X Multimedia Communication Processor with CIF 30fr/s MPEG-4/H.26X Bi-Directional Code,"

"Feed-Forward Dynamic Voltage Control Method for Low Power MPEG4 on Multi-regulated Voltage CPU,"

Website

http://www28.cs.kobe-u.ac.jp/

University

Tohoku University

Focus Area

Manufacturing
Systems & Architecture
Software for Multicore

Background

Masanori HARIYAMA received the B.E. degree in electronic engineering, M.S. degree in Information Sciences, and Ph.D. in Information Sciences from Tohoku University, Sendai, Japan, in 1992, 1994, and 1997, respectively.

Research Interest

Processor architecture for intelligent systems such as robots, Reconfigurable Computing,  High-level synthesis for VLSIs, Image processing

Research Publications

"Design of a CAM-Based Collision Detection VLSI Processor for Robotics", IEICE Trans. Elec.,Vol.E77-C,No.7,pp.1108-1115(1994)

"Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages",IEEE Transaction on Computers, Vol.54, No.6, pp.642-650(2005)

"Low-Power Field-Programmalble VLSI Using Multiple Supply Voltages", IEICE Trans. Fundamentals, Vol. E88-A, No.12, pp.3298-3305(2005)

"A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates", IEICE Trans. Electron., VOL.E89-C, No.11,pp.1655-1661(2006)

"VLSI Processor for Reliable Stereo Matching Based on Window-Parallel Logic-in-Memory Architecture", Digest of Technical Paper 2004 Symposium on VLSI Circuits VLSI Symposium, pp.166-169(2004)

"Fine-Grained Architectures for Field-Programmable VLSIs", 15th International Workshop on Post-Binary ULSI Systems, pp.1-5(2006)

"Processor Architecture for Road Extraction Based on Projective Transformation", Proc. SICE-ICCAS 2006, pp.1446-1450(2006)

"1000 frame/sec Stereo Matching VLSI Processor with Adaptive Window-Size Control", Proc. Asian Solid-State Circuits Conference (A-SSCC),pp.123-126(2006)

"FPGA Implementation of a Vehicle Detection Algorithm Using Three-Dimensional Information", Reconfigurable Architectures Workshop, CR-ROM, (2008)

"A Low-Power Field-Programmable VLSI Based on a Fine-Grained Power-Gating Scheme", IEEE International Midwest Symposium on Circuits and Systems, pp.702-705(2008)

Website

http://www.kameyama.ecei.tohoku.ac.jp/~hariyama/

University

Yokohama National University

Focus Area

Manufacturing

Background

Higher Education
1985, B.S., University of Science & Technology Beijing
1988, M.S., Yokohama National University
1992, Ph.D., Yokohama National University

Awards
Funai Award, 2005 JSME.
Best paper Award, 1997, JSME

Research Interest

Reliability Assessment and Design for Electronic Packaging
Micro-scale Measurement of Test for Micro-structure
Computer Aided Principle Design Methodology
Multi-Physical Design Support System

Research Publications

Mechanism of Damage Process on Si3N4/Cu Interface in Nanoscratch Test, Journal of Solid Mechanics and Materials Engineering, Vol.1, No.3 322-331, 2007.

A Study of Deformation Mechanism During Nanoindentation Creep in Tin-Based Solder Balls, Journal of Electronic Packaging, Vol. 129, No. 1, 71-75, 2007.

Fatigue reliability evaluation for Sn-Zn-Bi and Sn-Zn lead free solder joints, Materials Transactions, Vol.46, No.11, 2316-2321, 2005.

Evaluation of Diffusion Creep in Low Melting Point Materials by Nanoindentation Creep Test, JSME International Journal, SeriesA, Vol.49 ,No.3, 397-402, 2006.

Extraction Method for Physical Principles and Application to Static Behavior of Vehicle Suspension System Review of Automotive Engineering 26 4 439-446 2005

Optimization Approach for Reducing Sound Power from a Vibrating Plate by Its Curvature Design,; JSME International Journal,; Series C,; Vol.45,; No.1,; pp.87-98,; (2002.3).
 
Optimum Design of Vehicle Frontal Structure and Occupant Restraint System for Crash worthiness(A Multilevel Approach Using SDSS),; JSME International Journal Series A,; Vol.44,; No.4,; pp.594-601,; (2001).

Fatigue-Strength Prediction of Microelectronics Solder Joints Under Thermal Cyclic Loading IEEE Transactions on Components, Packaging, and Manufacturing Technology Part.A, Vol.20 3 266-273 1997

Website

http://www.me.ynu.ac.jp/faculty/process/yu/yu.html

University

Kyushu University

Focus Area

Systems & Architecture
Software for Multicore

Background

Tohru Ishihara received his B.S., M.S., and Ph.D degrees in computer science from Kyushu University in 1995, 1997 and 2000 respectively. From 1997 to 2000, he was a Research Fellow of the Japan Society for the Promotion of Science. For the next three years he worked as a research associate in VLSI Design and Education Center, the University of Tokyo. From 2003 to 2005, he stayed at Fujitsu Laboratories of America as a research staff of an advanced CAD technology group. In 2005, he returned to Kyushu University as an associate professor. His research interests include low power SoC design and low power embedded systems. He is a member of IEEE, ACM, IPSJ and IEICE.

Research Interest

Embedded processor, Multicore processor, Low power system

Research Publications

T. Ishihara, H. Yasuura, "Voltage scheduling problem for dynamically variable voltage processors," in Proc. of ISLPED 1998, pp.197-202, Aug., 1998.

T. Okuma, T. Ishihara, H. Yasuura, "Real-Time Task Scheduling for a Variable Voltage Processor," in Proc. of ISSS 1999, pp.24-29, Nov., 1999.

T. Ishihara, H. Yasuura, "A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors," in Proc. of DATE 2000, pp.617-616, Mar., 2000.

T. Ishihara, K. Asada, "An Architectural Level Energy Reduction Technique for Deep-Submicron Cache Memories" in Proc. of VLSI Design 2002, pp.282-287, Jan., 2002.

T. Ishihara, F. Fallah, "A non-uniform cache architecture for low power system design," in Proc. of ISLPED 2005, pp.363-368, Aug., 2005.

T. Ishihara, F. Fallah, "A cache-defect-aware code placement algorithm for improving the performance of processors," in Proc. of ICCAD 2005, pp.995-1001, Nov., 2005.

M. Sugihara, T. Ishihara, K. Murakami, "Task scheduling for reliable cache architectures of multiprocessor systems," in Proc. of DATE 2007, pp.1490-1495, Mar., 2007.

Website

http://www.slrc.kyushu-u.ac.jp/~ishihara/

University

Kyushu University

Focus Area

Systems & Architecture

Background

Education Background: B.E. Electric and Electronics, Federal University of Rio de Janeiro (UFRJ), Brazil, 1997; M.Sc. in Computer Science and Communication Engineering, Kyushu Univ., Japan, 2001; Ph.D. in Informatics, Kyushu Univ., Japan, 2007.

University Background: Teaching Assistant, Kyushu Univ., 2001-2004; Researcher, Kyushu Univ., 2002-2004; Post-doctoral Fellow and Research Assistant Professor, Kyushu Univ., 2008.

Industry Background: Researcher, Alberto Luiz Coimbra Institute - Graduate School and Research in Engineering (COPPE), 1998; Intern, Altius Solutions (now Cadence Design Systems Inc.), 2002; Researcher, Researcher, Fukuoka Laboratory for Emerging & Enabling Technology of SoC, 2005-2007; Researcher, Institute of Systems & Information Technologies/KYUSHU, Japan, 2007-2008

Research Interest

Computer Architecture (HPC, Memory Wall Problem), Low Power, Car Electronics (ECU, ITS), Reconfigurable Computing

Research Publications

GOULART FERREIRA, Victor Mauro et al. , REDEFIS - a System with a Redefinable Instruction Set Processor , Proc. of SBCCI-2006, p. 14 - 19, August, 2006, Brazil.

MURAKAMI, Kazuaki, GOULART FERREIRA, Victor Mauro. Just-in-Time HW/ISA/SW Co-optimization Techniques for SoC , SBAC-PAD 2004 Tutorial, Brazil, October, 2004.

GOULART FERREIRA, Victor Mauro, MURAKAMI, Kazuaki. Low Power Techniques through Dynamic Effective Precision Matching Computation (in Japanese) . Denshi Joho Tsushin Gakkai Ronbunshi, v.J86-C, n.8, p.817 - 825, 2003.

E, Burattini, M, de Gregorio, GOULART FERREIRA, Victor Mauro, FRANÇA, Felipe Maia Galvão. NSP: a Neuro-symbolic Processor. Lecture Notes in Computer Science , v.2687, p.9 - 16, 2003.

GOULART FERREIRA, Victor Mauro, YASUURA, Hiroto. Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-offs In: Intl. Symp. on Integrated Circuits and Systems Design (SBCCI), 2000, Manaus - AM. Proc. of the XIII SBCCI. IEEE, p.165 - 170, 2000.

SILVA, Gabriel P, CHAVES, Eliseu M., GOULART FERREIRA, Victor Mauro, ALVES, Vladimir C. An Analytical Area, Access and Cycle Time Model for On-Chip Multiported Memories Journal of Solid-State Devices and Circuits, Vol. 6, No. 1, p.27 - 23, February 1998.

E-mail

victor.goulart@acm.org