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Intel® Higher Education Program
2007 Asia Academic Forum
24th - 26th October, 2007: New Delhi, India
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Track Name: Software for Multi-Core    
     
Chairperson:  
 
 
     
Track Speakers:    
   

James Reinders

Chief Evangelist and Director of Marketing

James Reinders James is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including the world's first TeraFLOP supercomputer (ASCI Red), compilers and architecture work for a number of Intel processors and parallel systems. James Reinders is Chief Evangelist and Director of Marketing for Intel's Software Development Products. Reinders is the author of a new book "Intel Threading Building Blocks" from O'Reilly Media, monthly columnist for the "The Gauntlet" found online at go-parallel.com , and the author of the book "VTune Performance Analyzer Essentials" from Intel Press.




Presentation Title Exploiting Parallelism with Multi-core Technologies

Abstract:
With the emergence of multi-core processors, parallel processing is the new reality. By the end of 2007, nearly all the microprocessors Intel ships will be multi-core. As developers, we need to ask ourselves, "Are we prepared to program for parallel performance?" We all face challenges of scaling, debugging and maintaining threaded programs. This talk will discuss ways to overcome challenges as well as a few promising new tools and methods to help us turn multi-core power into application performance.

Milind Girkar

Principal Engineer

Milind Girkar Milind Girkar received a B.Tech. degree from the Indian Institute of Technology, Mumbai, a M.S. degree from Vanderbilt University, and a Ph.D. degree from the University of Illinois at Urbana-Champaign, all in computer science. Currently, he works in the Intel Compiler Group in SSG planning the development of the Intel compiler for future Intel processors. Before joining Intel, he worked on a compiler for the (first) UltraSPARC platform at Sun Microsysems. His e-mail is milind.girkar@intel.com






Presentation Title Compiler challenges for future computing platforms

Abstract:
The talk will present the evolution of compiler technology as it has changed to adapt to hardware. It will discuss the current state of the art in terms of compilation for today's systems, especially the features for multi-core support, and will explain some of the compiler challenges for future computing platforms.

Young Wang

Manager of XML engineering

Young Wang Young Wang is the manager of XML engineering in Intel Software and Solutions Group. His team is working to accelerate XML processing like XSLT transformation, parsing, schema validation and XPath query through software optimizations and hardware accelerations. He holds a master degree from Shanghai Jiaotong University, China. His major research area has been compilers, dynamic translations, Java virtual machines and fast XML processing used in SOA based applications.





Presentation Title Parallelized XML Processing

Abstract:
XSLT is increasingly being used for processing large XML documents. Existing implementation models are placing hard limits of the size of document that can be processed. We report on efforts to build an XSLT processor capable of handling Gigabyte sized documents with equivalent performance characteristics to the best known existing implementation models.

This work is largely driven by customer requests for large document handling where large is typically considered to be anything above the limits of existing implementations but below a size which mandates disk-based storage. For 32-bit systems this can be defined as approximately 0.3GB-2GB documents, allowing for processing and operating system memory overheads. In addition we find synergy between the needs of these types of processing and hardware XML parsers which do not interface easily to existing models.

The approach described is to employ a data representation which supports minimal inter-record linking to provide a small in-memory representation. A XSLT compiler is designed implemented to generate efficient processing of an XML document. Furthermore, the XLST transformation can be parallelized to reduce latency of processing large XML document. We compare this work to the performance achieved by the recently announced Intel® XSLT Accelerator Software library.

Suresh Srinivas

Principal Engineer

Suresh Srinivas Suresh Srinivas is a Principal Engineer in the Software Solutions Group within Intel Corporation where he is currently focused on new technology development using open source technologies. He has 15 years of experience developing language runtimes, tools, and compilers. During his career he has published over 15+ Peer Reviewed Articles and has 7 Patents pending. Prior to Intel he was at SGI leading their JVM efforts. He obtained his PhD in Computer Science from Indiana University specializing in tools and runtimes for parallel languages. While not working you can find him volunteering, cooking or hiking in the beautiful Pacific Northwest.




Presentation Title Concurrency Control in Managed Runtimes

Abstract:
The influential article "The Landscape of Parallel Computing Research: A View From Berkeley" suggests the path toward significantly faster CPUs is chip multiprocessing. Programmers will simply have to adapt by writing concurrent code, regardless of any consequential problems with threads. An important trend in application development is that new applications are being developed based on a Managed Runtime Environment (MRTE) such as Java or .NET. These languages provide features such as garbage collection and dynamic class loading that require a managed runtime system (i.e. the Java Virtual Machine (JVM) for Java and .NET for C#).

The Java programming language provides the synchronized construct and concurrent collections (java.util.concurrent) to facilitate the development of efficient and scalable concurrent programs. Recently Software Transactional Memory (STM) promises to alleviate the difficulty of programming using conventional mechanisms such as locks in a threaded environment. In this talk we will describe the work that we are doing within Intel in the Software Transactional Memory and compare this to the existing mechanisms in a threaded environment. Much of this work is based on open source Apache Harmony ( http://harmony.apache.org ) project that Intel is actively contributing to, we will describe this and point to areas for the University partners to innovate in.