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Intel® Higher Education Program
2007 Asia Academic Forum
24th - 26th October, 2007: New Delhi, India
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Track Name: Technology & Manufacturing
     
Chairperson:   Panel:
 
     
Track Speakers:    
   

TS Yeoh

Principal Engineer,
Assembly Test Manufacturing (ATM),
Test Operation

TS Yeoh Dr. TS Yeoh joined Intel in 1987 as a Product Quality & Reliability/Failure Analysis engineer working on microcontrollers. He then led the Q&R and Automotive product groups within the Product Development Quality & Reliability (PDQRE) department. This was followed with TS co-managing the PDQRE department from 1998-2002. He is currently a Principal Engineer from Assembly/Test manufacturing operations, with technical focus on Manufacturing & Device ESD (Electrostatic Discharge) and TRIZ (Theory of Inventive Problem Solving). While working, TS pursued his post graduate degrees from Universiti Sains Malaysia through part-time research. In 1989, he obtained his MSc in Solid State Physics and in 1997, his PhD in Applied Physics. He has also published a couple of papers in journals, internal and external conferences. These include IEEE International Reliability Physics Symposium, IEEE International Physical & Failure Analysis of IC Symposium, IEEE Transactions on Semiconductor Manufacturing Journal, Acta Crystallografica Journal, Journal of Physical Society of Japan and IEEE International Conference on Semiconductor Electronics.

Presentation Title Systematic innovation in Manufacturing - challenges/strategies

Abstract:
Nowadays, factories are faced with many challenges especially with the increased product complexity along with tightened quality, yield and productivity indicators. As engineers work on existing challenges, there is always the perception that sustaining activities in factories are mundane without any avenues to innovate. In order to address the multitude of challenges along with this perception, there needs to be a methodology, a tool, a philosophy, a culture which would help factories to overcome and make “Sustaining Cool”. This is the very reason why systematic innovation in the form of TRIZ was introduced.

TRIZ, a Russian acronym for Theory of Inventive Problem Solving, is a systematic approach to innovation based on the analysis of hundreds of thousands of patents. TRIZ provides in-depth understanding of the trends/patterns of evolution for technical systems. The theories and principles provided can help engineers solve problems and generate new concepts/systems. TRIZ is now an international Science of creativity that relies on the study of the patterns of problems and solutions, not just on the spontaneous creativity of individuals or groups. In summary, TRIZ is used for faster problem resolution, make “Sustaining Cool” and to help the engineers to be more creative and innovate. Solutions can be discovered even for problems which has been in existence for > 5 years. Below is a brief overview of some of the TRIZ tools.

One of the TRIZ tool is Functional Analysis where components of the equipment/system are identified and the interactions between them are defined. This enables the engineers to fully understand the details of their system. Then, the next tool i.e. Cause Effect Chain is used to discover the potential root causes. Here the questions “Why?” is asked until the fundamental limit of Science or equipment limitation is reached. Trimming tool is used to reduce/eliminate the components which would increased the efficiency and reduce the cost of the system. Another TRIZ tool is Contradictions and Principles. Contradiction is defined as “An improvement in one characteristic of a system results in the degradation of another characteristic”. Improving/Worsening parameters are categorized under 39 standard Parameters. Using the Contradiction Matrix, the appropriate Inventive Principles (40 Principles altogether) are identified and applied to solve the contradiction. Another tool is Trends of Engineering System Evolution is important as it enables one to think about the future and develop new ideas which are statistically reliable lines of evolution that describe natural transitions of systems from one state to another.

In summary, TRIZ is used for faster problem resolution and to help engineers to be more creative and innovate. The training which is provided is in the form of a 5-day Basic class. To-date, approximately 500 assembly/test manufacturing engineers have been trained. This is an ongoing process and will share the TRIZ concept, methodologies, tools, strategies and challenges with its implementation.

Jeff Pettinato

Senior Principal Engineer, Technology and Manufacturing Group
Automation Strategy & Pathfinding Manager, Assembly Test Technology Development
Intel Corporation

Jeff Pettinato Jeff Pettinato is a Senior Principal Engineer and the Automation Strategy and Pathfinding Manager in the Assembly Test Technology Development (ATTD) division at Intel. He is currently responsible for defining the strategic direction for Assembly-Test automation capabilities and driving technology pathfinding for future enabling technologies across a broad array of areas and capabilities that include: process control; engineering analysis; manufacturing cycle time optimization; equipment control and data flow optimization; factory scheduling and dispatching; and pre-competitive industry standards.

Jeff has held various technical, strategic, and management positions for Advanced Process Control (APC), Automated Material Handling Systems (AMHS), 300mm and 450mm wafer size conversion strategy and factory integration, and advanced equipment control. Since 2007, Jeff has been a member of the INEMI roadmap team for RFID and Assembly-Test manufacturing capabilities. From 2002 to 2006, he was an Intel representative to several International SEMATECH Manufacturing Initiative (ISMI) programs that drove industry direction for advanced 300mm factory capabilities and standards and strategic planning for the next wafer size conversion to 450mm. From 2000 to 2003, he chaired the International Technology Roadmap for Semiconductors (ITRS) Factory Integration working group. In 1997, he led the I300I consortia’s Computer Integrated Manufacturing (CIM) working group in partnership with Japan’s J300/SELETE consortia to deliver global standards for the 300mm wafer transition. This effort delivered ground breaking open industry standards for Process, Metrology and AMHS equipment control systems (software and communications) which is implemented into virtually all 300mm equipment manufactured today.

He received an Intel Achievement Award for his work on 300mm standards and equipment. He has authored or co-authored 18 technical papers and externally invited presentations in the fields of factory automation, open industry standards, and process control systems. He has been at Intel for 15 years and holds a master’s and bachelor’s degree in Electrical and Computer engineering with a specialization in robotics and control systems from George Mason University.

Presentation Title Highly Productive Assembly and Test Manufacturing in the Nano-Technology Era

Abstract:

Problem to Solve:
With the 300mm wafer size transition over the past 3-4 technology nodes, significant progress has been made in making Wafer Fabs more productive through the use of advanced automation systems that have been tightly integrated with efficient manufacturing processes and enabled through a transformation in process equipment. These automation systems include large advances made by the industry in the technology and use of Automated Material Handling Systems (AMHS), Process Control Systems (PCS), Scheduling and Dispatching systems, and manufacturing automation systems.

Over this same period, a significant amount of semiconductor product complexity has shifted to packaging, assembly and test, which has been driven by extreme variations in end user product needs from capability, I/O and form factor perspectives, as well as the more prevalent use of System-in-a-Package (SIP) to provide complete systems and subsystems. Per the ITRS, costs for package, assembly, test now account for greater than 50% of the cost of each chip produced. These business and environment changes have made chip assembly and test more challenging in order to achieve manufacturing cost efficiency with high quality.

Intel’s Assembly and Test Automation Strategy:
Starting at the 130nm technology node, Intel recognized this shift in product and manufacturing complexity and took steps to transform its manufacturing operating processes and automation capabilities to meet these emerging trends and ensure future cost effective manufacturing with high quality. The strategy has employed both reuse of capabilities that originated in 200mm and 300mm Fabs as well as new capabilities specifically tailored to meet an Assembly and Test (A-T) factory’s unique manufacturing needs. As a result, over the past 4 technology generations, Intel’s Assembly-Test factories now mirror and extend many of the advanced capabilities employed in its Fabs, especially with regard to data automation and analytics.

At a high level, these capabilities include the ability to:

  • lot tracking and execution control at equipment throughout the factory
  • control individual equipment and equipment modules at the factory level
  • set and read all recipes and tool parameters by remote control to eliminate miss processing
  • use of RFID on consumable materials to prevent excursions from incorrect or out of spec materials
  • accurate SPC and FDC from metrologies/sensors to catch and fix process drifts or identify out of control equipment
  • lot kitting and dispatch capabilities to enable efficient equipment use and faster cycle times
  • tracking of equipment performance data to drive efficient utilization and identify issues that must be fixed

Figure 1 shows a blueprint for productive A-T Factories with high quality output using targeted automation capabilities, while Figure 2 shows the progressive build-out of SPC, Equipment Performance Tracking and Unit Level Metrology.

Equipment Automation Capabilities Form the Base:
Process and metrology equipment are the foundation to all successful, highly automated, and productive factories. To meet the overall strategy, assembly and test equipment at Intel factories have a strong base level of capabilities which enable high quality and productivity at a factory level.

These capabilities and requirements for equipment and linked equipment modules include:

  • continuous flow, non-stop operation
  • 100% data accuracy
  • rapid recovery following an embedded controller crash and the ability to reset using persistent data
  • remote diagnostics connectivity
  • meet virus & cyber security guidelines
  • no automation impact to tool run rates
  • standard load ports using JEDEC standards
  • standard data connection using SEMI standards (E5, E30, and E37) and common alarms and events across a supplier’s various equipment types
  • automated equipment performance tracking using SEMI standards, including SEMI E10, E58, and E116

What This Presentation Will Provide:
In this presentation, we look at a revolution that has occurred at Intel over the past 3-4 technology nodes to make packaging, assembly, and test manufacturing more productive and efficiency through the use of advanced automation capabilities. We will provide an overview of the business and product drivers that have shaped Intel strategy in manufacturing and automation and then provide a detailed examination of the systems and capabilities that have been progressively implemented technology generations to meet these needs. Finally, the authors will conclude with some actions that the industry can take to drive lower cost manufacturing in the future through pre-competitive standards and other industry initiatives.

Figures:

Blueprint for Productive A-T Factories with High Quality Output Using Targeted Automation Capabilities

Proliferation Build-out for SPC, Equipment Performance Tracking and Unit Level Metrology

G Sreenivas

General Manager
Technology Manufacturing Group, India (TMG-I)
Intel Technology India Pvt. Ltd., Bangalore, India

G Sreenivas Sreenivas is the General Manager of Technology Manufacturing Group-India. He joined Intel in 2001 and currently manages the group at India that provides Automation Solutions to Intel’s Fab/Sort/Assembly/Test Manufacturing operations.

Additionally, he is also responsible for the group that is involved in delivering design and technology solutions that ensure Intel's leadership in product development and silicon technology. Before this, he was a Process Engineering Manager at Fab22 and was involved in multiple process technology start-ups and ramp cycles leading several technology development and transfer efforts. Prior to joining Intel Corporation, he was involved in process development, productization, manufacturing, and technology transfer of DLP (Digital Light Processing) products and advanced CMOS process technology research at Texas Instruments Inc at Dallas, TX.

Sreenivas has Masters and Ph.D. degrees in Electrical Engineering and an MBA. He has been engaged in research and development, and manufacturing processes/methods in the area of microelectronics for over 16 years. He holds United States Patents and has regularly published scores of papers in reputed international journals and presented papers in the field of microelectronics/device physics.

Presentation Title Challenges & Oppprtunities in Electronic Packaging

Abstract:
Historically, the primary function of microprocessor packaging has been to facilitate electrical connectivity of the complex silicon chips to the printed circuit board, while providing mechanical protection to the chip from the external environment. However, as microprocessor performance continues to follow Moore’s law, various levels of integration becomes necessary to meet the needs of different market segments. Thus, electronics packaging continues to include expanding and evolving topics and technologies, as the demands for smaller, faster, and lighter products continues without signs of abatement. These demands mean that individuals in each of the specialty areas involved in electronics packaging-such as electronic, mechanical, and thermal designers, and manufacturing and test engineers-are all interdependent on each others knowledge. The art and science of semiconductor packaging has advanced radically over the past decades as faster, more powerful, and cheaper computing devices with tens of millions of transistors continue to become a necessity. These advances require and will continue to require significant advances in the areas of mechanical integrity, signal integrity, power delivery and power dissipation, with constant market driven cost pressures. Recent trends in nano-technologies, system-on-a-chip vs. system-in-a-package, advanced analysis / simulation tools and metrologies will also need to be comprehended.

The packaging of electronic devices and systems represents a significant challenge for technologists. Performance, efficiency, cost considerations, dealing with the newer IC packaging technologies, and EMI/RFI issues all come into play. Thermal considerations at both the device and the systems level are also necessary. This presentation will focus on a broad perspective of the challenges and in better quantifying and understanding issues of very high speed signaling, high density interconnects, efficient power delivery, and heat dissipation/thermal management. The recent advances and future needs of technology solutions in this field will be discussed with reference to opportunities in the following disciplines: Interfacial mechanics and fracture, electronic materials and polymer science, computational and experimental methods in electromagnetics, signal integrity, thermal sciences and advanced manufacturing.