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Rob Crooke

Vice President, General Manager,
Business Client Group

Rob Crooke Robert Crooke is vice president and general manager of the Business Client Group (BCG). He is responsible for directing Intel's vision for delivering innovative business client solutions and is responsible for the definition, development, and marketing of Intel's desktop platform solutions.

Previously, Crooke served as vice president and general manager of the Desktop Product Group, leading the marketing and planning of Intel's desktop products and initiatives. This includes the processors and chipset product roadmaps as well as digital home and digital office initiatives. From 2000 to 2004 Crooke was general manager of the Platform Architecture and Solutions Division. In this role he was responsible for the company's development of motherboard products in addition to desktop microprocessor and chipset enabling technology, which includes reference platforms, as well as electrical and thermal mechanical solutions. Crooke has served as director of marketing for the Basic Microprocessor Division and Performance Microprocessor Division. He joined Intel in 1989 in the sales force as a field applications engineer and spent nine years in the field in various roles.

Crooke is a frequent speaker at industry events, including the Intel Developer Forum, Communication Board of Directors, Game Developers Conference and the Consumer Electronics Show. Prior to joining Intel, he held design engineering positions at Alliant Computer Systems and Custom Silicon Inc. He received his bachelor's degree in computer systems engineering from the University of Massachusetts in 1985.

Presentation Title Beyond the blackboard: Technology and Teaching in the 21st Century

Abstract:
Technology is dramatically changing the knowledge being produced in the world today. These technological changes, which will be as fundamental as the introduction of blackboards into the classroom two centuries ago, will test the academic structures around the world. Intel has established a leadership role with the World Ahead Program to offer a scalable and cost effective solution for developing nation academic structures. Mr. Crooke will discuss the importance of accelerating access to the World Ahead Program technologies and how these new Intel innovations will focus on building 21st century skills for today’s children, today’s educators and tomorrow’s working citizens.

Kevin Zhang

Intel Fellow and Director of Advanced Memory Circuit
and Technology Integration at Intel Technology & Manufacturing Group

Kevin Zhang Kevin Zhang is an Intel Fellow and Director of Advanced Memory Circuit and Technology Integration at Intel Technology & Manufacturing Group. He is responsible for Intel's embedded memory technology development for future products. Zhang has led the design and validation of technology lead vehicles for both future process and product development from 90nm to 45nm generations at Intel. Zhang received his BS degree from Tsinghua University in 1987 and his PhD degree from Duke University in 1994, both in Electrical Engineering.





Presentation Title Extending Moore's Law with Innovations in Nano-scale CMOS Technologies

Abstract:
Moore's law has been the guiding principal for semiconductor industry over last 40 years. The relentless technology scaling has reduced the feature size of transistor well blow 50nm regime in today's CMOS technology and the scaling has led to an unprecedented level of integration in VLSI system design in achieving ever higher performance and lower power consumption. As the physical dimensions of transistors are scaled down to nano-scale, there are many new challenges facing the industry. This talk will first discuss the key challenges facing today's technology scaling, including transistor leakage management, process variations and design for manufacturing (DFM). Some innovative technology solutions such as strained Si and 3D transistors will be used to illustrate how to address the technology challenges. The presentation will also discuss how to explore the process-design co-optimization in overcoming these difficulties. Several real technology-product optimization examples, including high-frequency clock tree design and large on-die SRAMs, will be presented on how to mitigate the scaling challenges and achieve optimal product design goals.

Vivek De

Intel Fellow and Director of Circuit Technology Research
in Intel’s Circuits Research Lab (CRL)

Vivek De Vivek De is an Intel Fellow and Director of Circuit Technology Research in Intel’s Circuits Research Lab (CRL). He provides strategic direction for future circuit technologies and is responsible for aligning CRL’s circuit research with technology scaling challenges. He has published 151 technical papers in refereed conferences and journals, and 6 book chapters in the areas of low power and high performance circuits. He holds 129 patents, with 64 more patents filed (pending). Vivek received his Bachelor’s degree in electrical engineering from the Indian Institute of Technology in Madras, India in 1985 and his Master’s degree in electrical engineering from Duke University, Durham, North Carolina in 1986. He received a Ph.D. in electrical engineering from Rensselaer Polytechnic Institute (RPI), Troy, New York in 1992.

Presentation Title Energy-Efficient Terascale Computing in Nanoscale Technology: Emerging Challenges and Opportunities

Abstract:
We will present emerging opportunities to scale new heights in energy-efficiency and cost-effectiveness, and achieve terascale performance levels. We will show how this can be achieved by (1) continued Moore’s Law technology evolution into nanoscale regimes; (2) innovative many-core processor architectures containing general-purpose cores, special-purpose engines & efficient on-die interconnect networks; and (3) exploiting the tremendous levels of parallelism in future mainstream applications. We will discuss the challenges and opportunities to enable fast, efficient and fine-grain performance & power management in many-core processors. We will show how designs with multiple independently controlled supply and frequency domains can provide unprecedented levels of energy management capabilities, variation tolerance, reliability and resiliency. We will highlight the barriers & promising solutions to achieving ultra-low-voltage operation and pushing the thermal envelope, both of which are critical for widening the range of dynamic voltage & frequency scaling in future processors.

Valluri R. Rao

Intel Fellow, Technology and Manufacturing Group
Director, Analytical and Microsystems Technologies
Intel Corporation

Valluri R. Rao Valluri Rao pioneered a new infrastructure for VLSI IC characterization which is used for silicon debug and yield improvement of Intel’s Microprocessor Products. New technology was developed in R&D labs at Intel and equipment was developed in collaboration with semiconductor equipment suppliers. This infrastructure was proliferated throughout Intel’s worldwide Design, Assembly & Test and Manufacturing Fabs in addition to being adopted by the semiconductor industry at large. Rao was elected to Intel Fellow in the Technology and Manufacturing Group for these accomplishments.

The technology developed included, Electron-Beam Voltage Contrast testing, Magneto-Optic testing for on-chip current measurement from microprocessor power busses, Ultra Fast electro-optic testing for through silicon waveform measurements, Infra Red through silicon emission microscopy, and Focused Ion Beam and laser silicon micromachining methods for on-chip reconfiguring of CMOS circuits. In addition, collaterals such as CAD navigation to locate circuits on a chip, and sample preparation were also developed. Design-For-Test features, to enable optimal use of the capabilities on products, were co-developed with product design and CAD groups and implemented in the chip designs.

Also, roadmaps were created and executed to ensure that the characterization capabilities kept pace with Moore’s Law of scaling. Rao was involved in utilizing this infrastructure on 9 generations of Intel Microprocessors through circuit characterization, silicon debug, and yield improvement.

Rao initiated Intel’s early work on optical interconnects as a direct extension of the optical measurement work on Silicon. Also, Rao established and built up Intel’s MEMS research program in the early 2000s as an extension of the silicon micromachining for CMOS circuit reconfiguring. This program researched and developed applications of MEMS to Intel’s wireless technology for multimode and reconfigurable radios through the fabrication of MEMS RF switches integrated with RF passives in a CMOS process. Currently Rao is researching novel memory materials and MEMS to create high density storage solutions for Intel platforms.

Rao was awarded three Intel Achievement awards (Intel's highest technical award), has 62 issued patents, over 30 publications, and has given numerous invited lectures.

Rao graduated from Cambridge University, UK (Jesus College & Engineering Department) with BA, MA and Ph.D. degrees in Electrical Engineering. He also worked as a post doctoral research fellow at Cambridge prior to joining Intel in 1983. Rao was born in Andhra Pradesh, India.

Presentation Title A Review of Emerging Memory Technologies

Abstract:
Current Non Volatile Memory technologies are primarily based on floating gate flash (both NOR and NAND). Looking into the future new memory concepts, materials and device structure are being researched to overcome the challenges of continued scaling of flash memory. Many new candidates have emerged, including Phase Change, Ferro-Electric, Magnetic and MEMS based probe storage memories to name but a few. This talk will describe some of these alternative memory technologies that researchers are pursuing and also the challenges associated with them.

Raj Yavatkar

Intel Fellow and Director of the Platform Validation Architecture
in the Digital Enterprise Group

Raj Yavatkar Dr. Raj Yavatkar is an Intel Fellow and Director of the Platform Validation Architecture in the Digital Enterprise Group. He leads the efforts to introduce design/validation technology innovations to reduce the silicon and platform validation complexity. Dr. Yavatkar led the formation of the Systems Technology Lab involved in advanced R&D in the areas of system architecture and platform technologies. From 1999 through 2004, he was the Chief Software Architect for Intel's IXP family of network processors.

Dr. Yavatkar received his Ph.D. in Computer Science from Purdue University in 1989 and holds thirteen patents, with more than 25 pending. He is recognized as a leading expert in the networking industry, is an Editor of IEEE Network Magazine, and is the General Chair of ACM/IEEE Sponsored ANCS 2007. Dr. Yavatkar has published more than 30 papers in academic journals and conferences and has co-authored the book, Inside the Internet's Resource Reservation Protocol (RSVP) published by John Wiley.

Presentation Title SoC architectures in TerraScale world: Challenges and Opportunities

Abstract:
With continued transistor scaling and ability to put billion+ transistors on the die, multi-core computing has gone mainstream. That includes an increasingly SoC (System on a Chip) architecture that integrates many different components. By putting 10s of multi-threaded processor cores on a die, the computing industry will soon deliver TeraScale system performance on every desktop. However, such a potential also brings with it an interesting set of challenges in the areas of design/validation, reliability, and computer system architecture, and support for emerging applications. The talk will describe these research challenges as well as potential directions for addressing them.

Mary Smiley

Director, Emerging Platforms Lab (EPL),
Corporate Technology Group

Mary Smiley Mary Smiley is the Director of the Emerging Platforms Lab at Intel Corporation. She leads the cross geography lab in pioneering research to conceive, architect, and prototype ultra mobile devices that offer rich understanding of a person and their environment and to explore health technology for emerging markets.

Throughout her career at Intel, Mary has led the design, development, and implementation of a variety of cutting edge research technologies delivering to a variety of Intel groups and external parties. She drove collaboration with TV Networks (ABC, NBC, Discovery, Scripps, Game Show Network), TV listing provider Tribune Media Services (TMS) and device manufacturers (Evolve Communications) to introduce the concept of interactive television – enabling a user to connect with television programming via Internet interactivity. She delivered Enhanced Television solutions such as NBA Pick n’ Play (on demand Internet streaming of NBA events) and The Greeks (educational program w/post show interactive PC content) and a multi-point audio conferencing solution MARS – to 3rd party CenterSpan. She delivered Intercom software (home audio networking) to Intel’s Home Networks Operation released to consumers along with Intel AnyPoint™ Home Network products. Other areas of research included leading programs on platform virtualization, partitioning, reliability and scalable I/O virtualization. Mobile device characterization, provisioning and management.

Prior to joining Intel, Mary was a senior software engineer at Lockheed Missiles & Space. She contributed to the Hubble Space Telescope (HST) Program developing knowledge engines for analysis of HST telemetry to assess health of the vehicle and predict trending towards component failure. She contributed to the successful first servicing mission of HST (which compensated for optics dysfunction by installing corrective optics h/w & s/w).

Mary holds a Bachelor of Science from University of Iowa and a Masters of Engineering in Engineering Science from Penn State University.

Presentation Title Mobility - Redefined

Abstract:
Mobile computing in the future - is it just about laptops getting smaller or handhelds getting bigger screens? More of the same - Internet access, productivity applications, mail, calendar? Or is this just the tip of the iceberg? Are there new applications, new usages, new experiences that make mobile computing a more integral fabric of every aspect of our lives? Can machines do more than what they are told to do? Can they bridge the digital and the physical world, be aware of more than just the user's command, anticipate and act on behalf of the user? Can they be more than entertainment or productivity tools? Can they enrich all aspects of lives, going beyond work and play? How do we make this future real? What are the key technical challenges that need to be addressed? What advances are making this future happen? Come listen to Mary Smiley, Director of Intel's Emerging Platforms Lab, talk to the future of the mobile experience from Intel's perspective.

Ajay Bhatt

Intel Fellow and Chief I/O Architect,
Digital Enterprise Group

Ajay Bhatt Ajay Bhatt is an Intel Fellow in the Digital Enterprise Group and chief I/O architect. Bhatt is responsible for future platform and I/O interconnects directions for Intel. This role involves leading the definition of next-generation Application Accelerator Architecture called Geneseo and I/O technologies across the market segments internally and within the industry.

Bhatt is an industry-recognized expert in I/O technologies and was instrumental in the development and proliferation of USB, AGP4X and PCI Express as ubiquitous industry standards. Bhatt joined Intel in 1990 as a senior staff architect on the chipset architecture team in Folsom.

Bhatt received his bachelor’s degree in electrical engineering from the M.S. University, Baroda, India, in 1980. He received his master’s degree from The City University of New York in 1984. Bhatt holds nine U.S. patents and has few patents in various stages of development.

In 1998, 2003 and 2004 Bhatt was nominated to take part in a Distinguished Lecture Series at leading universities in the United States and Asia. He received an Achievement in Excellence Award for his contribution in PCI Express specification development in 2002. Bhatt is Fellow-in-residence for Intel India.

Presentation Title Acceleration with Many-cores & Special Purpose Hardware

Abstract:
Moore’s law has enabled the current trend toward multi-core computing that is dramatically increasing performance and power efficiency. This can continue for at least the next 10 years, but not following the same path as the last 25. We have challenges in scaling the silicon technology, e.g., in power and signaling. We have challenges in scaling microarchitecture, e.g., how much parallelism can we extract from a single thread. Neither hardware nor software alone can solve all the issues in these new challenges.

As computing requirements become more complex, new strategies evolve to provide the performance necessary for data- and calculation-intensive applications. A growing such strategy is the use of specialized accelerators to enhance the performance of specific tasks or functions. Examples of emerging applications for which accelerators may be suitable are photorealistic graphics, financial simulation, and climate modeling. The development of specialized application accelerators is happening today. However, they do not share a common attach point, and have no common architecture or programming model. An industry framework that economically and efficiently enables specialized acceleration is highly desirable. This talk will focus on a new architectural framework for the attached application accelerators called Geneseo. The talk will provide an overview of the Geneseo interconnect and software architecture and provide insight in to proposed improvements in available bandwidth, latency, efficiency and software interface.

Geoff Lowney

Intel Fellow, Software Solutions Group, and
Director of Compiler and Architecture Advanced Development

Geoff Lowney Geoff Lowney is an Intel Fellow, Software Solutions Group, and Director of Compiler and Architecture Advanced Development. He is responsible for using advanced compiler technology to improve the performance and usability of Intel Architecture processor family products.

Lowney joined Intel as part of a June 2001 agreement with Compaq Computer Corporation that called for the transfer of microprocessor engineering and design expertise to Intel. Prior to joining Intel, he was a Compaq Fellow and Director of Compiler and Architecture Development for the Alpha Microprocessor Group. His responsibilities included developing compiler technology and tuning compilers for Alpha systems, providing architectural direction to the microprocessor design teams and designing Alpha architecture extensions.

Before joining Digital Equipment Corporation in 1991, Lowney was a Consulting Engineer at Hewlett-Packard from 1990 to 1991. From 1984 to 1990, he was Director of Compiler Development at Multiflow Computer.

Lowney received his doctorate and master's degrees in computer science and his bachelor's degree in mathematics from Yale University in 1983, 1978 and 1975, respectively.

Presentation Title Software for multi-core processors.

Abstract:
Future processors developed by Intel will have more than one core on a die. Multi-core processors will bring tremendous computing power to the desktop PC, enabling new classes of applications.  These applications will be written using parallel programming techniques.  In this talk I will present the tools Intel has developed to support parallel programming and discuss some of the ideas we are exploring to enable wide-spread adoption of parallel programming.

Tom Rampone

Vice president of Sales and Marketing Group and
General Manager of the Channel Platforms Group

Tom Rampone Thomas A. Rampone is vice president of Sales and Marketing Group and general manager of the Channel Platforms Group. As one of Intel channel chiefs, Rampone leads a worldwide channel organization whose charter is to develop innovative products that meet the unique needs of the emerging markets worldwide and to deliver platform ingredients and solutions to broad channel and local OEM (original equipment manufacturers) customers.

Prior to this position, Rampone was general manager of the User-Centered Platform Solutions Division. He managed the development of Intel's desktop platforms, motherboard products and related industry and technology initiatives. Previously, Rampone was director of the Intel Desktop Boards Operation, where he was responsible for development, delivery and support of Intel's desktop board products. Rampone joined Intel in 1984 as a test development engineer, followed by several engineering and management positions in board design and development.

Rampone, who holds seven patents, received his BSEET from the Oregon Institute of Technology in 1984.

Presentation Title CMPC - Integrating Technology for Local Markets

Abstract:
There are about 900,000,000 enrolled students in the world and most are still being taught with 19th century learning models. What’s remarkable is how useful these methods still are today as they reflect more than 2000 years of teaching and learning common to most people around the world. Educational systems have been reticent to adopt computing despite its promise – and demonstrable value in many other venues. As a result, very few students make use of computing in their everyday school experience at this time. But this changing: global attention linking education to economic productivity and new technologies have awakened and renewed the possibility of effectively incorporating the benefits of computing into the pedagogical experience. By understanding classrooms as complex systems we can begin to understand the necessary nuance and systemic subtlety associated with incorporating 21st century technologies within the constructs of centuries old teaching methodologies – and do so effectively enhancing the total classroom experience for both teachers and students. I will talk about the development of the our currently available Intel Powered Classmate PC for schools and specifically call out areas where technological innovation can support the students and teachers in ways appropriate to the classroom, enhancing the value of the educational experience in today’s world.

Andrew Chien

Vice President of Intel Research

Andrew Chien Andrew A. Chien is Vice President and Director of Intel Research. Dr. Chien has responsibility for Intel's exploratory research activities including Intel's innovative network of lablets in Berkeley, Pittsburgh, and Seattle. Intel Research is involved in a broad spectrum of exploratory research including computer circuits, architectures, distributed systems, sensors, robotics, networking, communications, ubiquitous computing, emerging markets and the user experience.

From 1998 to 2005, Chien served as the SAIC Endowed Chair Professor in computer science and engineering, and the founding Director of the Center for Networked Systems (CNS) both at the University of California at San Diego (UCSD). From 1990 to 1998, Chien was a professor in computer science and senior scientist at NCSA at the University of Illinois at Urbana-Champaign. Chien received his B.S. in Electrical Engineering and M.S. and Ph.D. in Computer Science, all from the Massachusetts Institute of Technology.

For more than 20 years, Chien has been a global leader in research and the development of high-performance computing systems. His expertise includes networking, Grids, high performance clusters, distributed systems, computer architecture, high speed routing networks, compilers, and object oriented programming languages. Chien has been recognized as an NSF Young Investigator, ACM Fellow and IEEE Fellow.

Presentation Title Exploratory Research: Essential Computing – Computing for the Essence of our Lives

Abstract:
Next generation computing systems will move from task and utility-orientation to supporting the essence of our lives.  Intel Research’s “Essential Computing” vision is driving a broad-based effort to create applications and systems technologies to simplify and enhance all aspects of our work and daily life.  We will describe the Intel Research organization, our vision for essential computing, and highlight our research themes which increase capabilities for computing systems to have personal awareness, be richly communicative, exhibit physicality, conceal complexity, and couple with biological systems.   A selection of current research projects and opportunities in these areas will be described.