Faculty Biographies

Kazuaki Murakami was born in Kumamoto, Japan in 1960. He received the B.E., M.E., and Ph.D. degrees in computer science and engineering from Kyoto University, Japan in 1982, 1984, and 1994, respectively. From 1984 to 1987, he worked for the Fujitsu Limited, where he was a Computer Architect of the mainframe computers. In 1987, he joined the Department of Information Systems of Kyushu University, Japan. He is currently a Professor of the Department of Informatics, and also the Director of the Information Infrastructure Initiative and the Research Institute for Information Technology of Kyushu University. He is a member of the ACM, the IEEE, the IEEE Computer Society, the IPSJ (Information Processing Society of Japan), and the JSIAM (Japan Society for Industrial and Applied Mathematics).

Advanced SoC architectures, High-performance computing, High-performance and low-power embedded systems

Kazuaki MURAKAMI, Morihiro KUGA, Naohiko IRIE, Shinji TOMITA, "SIMP (Single Instruction stream/Multiple instruction Pipelining): A Novel High-Speed Single Processor Architecture, " Proc. of IEEE-CS & ACM 16th Annual International Symposium on Computer Architecture , pp.78-85, May 1989.

Kazuaki MURAKAMI, Shin-ichiro MORI, Akira FUKUDA, Toshinori SUEYOSHI, Shinji TOMITA, "The Kyushu University Reconfigurable Parallel Processor - Design of Memory and Intercommunication Architectures -," Proc. of ACM-SIGARCH 1989 International Conference on Supercomputing , pp.351-360, June 1989.

Tetsuo HIRONAKA, Takashi HASHIMOTO, Keizo OKAZAKI, Kazuaki MURAKAMI, Shinji TOMITA, "A Single-Chip Vector-Processor Prototype Based on Multithreaded Streaming/FIFO Vector (MSFV) Architecture," Proc. of International Symposium on Supercomputing'91 , pp.77-86, Nov. 1991.

Takashi HASHIMOTO, Kazuaki MURAKAMI, Tetsuo HIRONAKA, Hiroto YASUURA, "A Micro-vectorprocessor Architecture - Performance Modeling and Benchmarking -," Proc. of ACM-SIGARCH 1993 International Conference on Supercomputing , pp.308-317, July 1993.

Kazuaki MURAKAMI, Satoru SHIRAKAWA, Hiroshi MIYAJIMA,"Parallel Processing RAM Chip with 256Mb DRAM and Quad Processors," Digest of Technical Papers, 1997 IEEE International Solid-State Circuits Conference , FP14.3, Feb. 1997.

Taku OHSAWA, Koji KAI, Kazuaki MURAKAMI, "Optimizing the DRAM Refresh Count for Merged DRAM/Logic LSIs, " Proc. of International Symposium on Low Power Electronics and Design (ISLPED'98) , pp.82-87, Aug. 1998.

Koji INOUE, Koji KAI, Kazuaki MURAKAMI, "Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs," Proc. of the IEEE 5th International Symposium on High-Performance Computer Architecture (HPCA-5) , pp.218-222, Jan. 1999.

Koji INOUE, Tohru ISHIHARA, Kazuaki MURAKAMI, "Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption," Proc. of International Symposium on Low Power Electronics and Design (ISLPED'99) , pp.273-275, Aug. 1999.

Koji HASHIMOTO, Hiroto TOMITA, Koji INOUE, Katsuhiko METSUGI, Kazuaki MURAKAMI, Nobuaki MIYAKAWA, Shinjiro INABATA, So YAMADA, Hajime TAKASHIMA, Kunihiro KITAMURA, Shigeru OBARA, Takashi AMISAKI, Kazutoshi TANABE, Umpei NAGASHIMA, Kiyoshi HAYAKAWA, "MOE: A Special-Purpose Parallel Computer for High-Speed, Large Scale Molecular Orbital Calculation," Proc. of 1999 Supercomputing (SC99) , Nov. 1999.

Koji INOUE, V. G. MOSHNYAGA, Kazuaki MURAKAMI, "A History-Based I-Cashe for Low-Energy Multimedia Applications," Proc. 2002 International Symposium on Low Power Electronics and Design (ISLPED'02) , pp.148-153, Aug. 2002.

Koji INOUE, V. G. MOSHNYAGA, Kazuaki MURAKAMI, "A Low Energy Set-Associative I-Cashe with Extended BTB," Proc. 2002 International Conference on Computer Design (ICCD'02) , pp.187-192, Sept. 2002.

Hamid NOORI, Farhad MEHDIPOUR, Kazuaki MURAKAMI, Koji INOUE, Morteza Saheb ZAMANI, "A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor," IEEE International Conference on Field Programmable Logic and Applications (FPL'06) , pp.781-784, Aug. 2006.

Hamid NOORI, Farhad MEHDIPOUR, Kazuaki MURAKAMI, Koji INOUE, M. GOUDARZI, "Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor," The European Event for Electronic System Design & Test (DATE'07), Apr. 2007.

arch-staff@c.csce.kyushu-u.ac.jp

http://www.c.csce.kyushu-u.ac.jp/~murakami/

• Reconfigurable analog RF circuits for SDR and cognitive radio
• Millimeter-wave circuits
• On-chip MEMS variable inductors
• GHz interconnect technology in Si ULSI
• Modeling and optimization of on-chip spiral inductors
• Signal integrity of high-speed digital circuits
• Modeling of process fluctuation and statistical static timing analysis (SSTA)

• Hiroyuki Ito, Makoto Kimura, Kenichi Okada, and Kazuya Masu, "A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers," IEEE Symposium on VLSI Circuits, pp.136-137, Kyoto, Japan, June 2007. (invited to JSSC)
• Yusaku Ito, Hirotaka Sugawara, Kenichi Okada, and Kazuya Masu, "A 0.98 to 6.6GHz Tunable Wideband VCO in a 180nm CMOS Technology for Reconfigurable Radio Transceiver," IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 359-362, Hangzhou, China, Nov. 2006. (Best Design Award and invited to ISSCC presentation)
• Takeshi Ito, Daisuke Kawazoe, Kenichi Okada, and Kazuya Masu, "A DC-7GHz Small-Area Distributed Amplifier Using 5-port Inductors in a 180nm Si CMOS Technology," IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 363-366, Hangzhou, China, Nov. 2006. (Best Design Award Nominee)
• Kenichi Okada, Hirotaka Sugawara, Hiroyuki Ito, Kazuhisa Itoi, Masakazu Sato, Hiroshi Abe, Tatsuya Ito, and Kazuya Masu, "On-Chip High-Q Variable Inductor Using Wafer-Level Chip-Scale Package Technology," IEEE Transactions on Electron Devices, Vol. 53, No. 9, pp. 2401-2406, Sep. 2006.
• Yusaku Ito, Yoshiaki Yoshihara, Hirotaka Sugawara, Kenichi Okada, and Kazuya Masu, "A 1.3-2.8 GHz Wide Range CMOS LC-VCO Using Variable Inductor," IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.265-268, Nov. 2005.
• Hiroyuki Ito, Junpei Inoue, Shinichiro Gomi, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "On-Chip Transmission Line for Long Global Interconnects," IEEE International Electron Devices Meeting (IEDM), pp.677-680, 2004.
• Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "Differential Transmission Line Interconnect for High Speed and Low Power Global Wiring," IEEE Custom Integrated Circuits Conference (CICC), pp.325-328, 2004.
• Kazuhisa Itoi, Masakazu Sato, Hiroshi Abe, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu, and Tatsuya Ito, "On-Chip High-Q Cu Inductors Embedded In Wafer-Level Chip-Scale Package for Silicon RF Application," IEEE MTT-S International Microwave Symposium (IMS), pp.197-200, 2004.
• Hidenari Nakashima, Junpei Inoue, Kenichi Okada, and Kazuya Masu, "ULSI Interconnect Length Distribution Model Considering Core Utilization," Design Automation and Test in Europe (DATE), No.2, pp.1210-1215, 2004.
• Kenichi Okada, Kento Yamaoka, and Hidetoshi Onodera, "A Statistical Gate-Delay Model Considering Intra-Gate Variability," IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp.908-913, 2003.