Included on this Page:

Mr. Anwar Ali Mr. Richard A. Tyo Dr. Ruby dela Torre Mr. Nik Zurin Mr. Kin Gan

Operational Modeling Senior Staff Engineer
Operational Decision Support Technology – Malaysia,
Assembly Test Manufacturing (ATM)

Anwar Ali is a Senior Staff Engineer in ODST (Operational Decision Support Technology) Malaysia. He leads a team of Operations Research practitioners in applying discrete event simulation and optimization techniques to assist ATM factories in applying quantitative decision support and analysis methods, mainly to improve productivity. Anwar also collaborates with Malaysia universities in initiatives to apply science to manufacturing. Anwar holds a Masters degree in Decision Science. He has been in Intel for 16 years.

Presentation Title Challenges in Manufacturing Modeling Presenter Name Anwar Ali Job Title Operational Modeling Sr. Staff Engineer

Abstract:
A brief overview of High Volume Manufacturing (HVM) research goals and ongoing projects is given. The future direction and challenges faced by Assembly Test Manufacturing (ATM) are shared. These include trying to get the most from the tools and space and reduce headcount while ATM complexity is increasing. Finally, research collaboration opportunities in manufacturing modeling are discussed.

Principal Architect
Enterprise Solution Sales (ESS), Software & Solutions Group (SSG)

Richard has been with Intel for over nine years and is a Principal Architect in Enterprise Solutions Sales (ESS), where he is responsible for definition of enterprise architectures using Intel platforms and products to solve customer needs, providing customer-facing technical sales support, mentoring of Solutions Architects in the field worldwide, and developing advanced architectural designs and pilots for RFID and wireless sensor network applications.

He has served as a Manufacturing Research Integrator and TME Technologist in Intel´s Technology Manufacturing Engineering (TME) group, and is recognized as a Subject Matter Expert in RFID. Richard was a charter member of the TMG RFID Program Management Office (PMO), where he was: (1) Lead for RF Engineering, Technical Standards, and Government Affairs, and (2) Lead for Assembly/Test Manufacturing RFID projects. Richard has performed path finding, development, and integration of multiple factory automation and supply network support systems, including proof-of-concept projects for manufacturing and supply chain operations utilizing wireless, RFID, mote, and smart object technologies. Richard is a member of the Intel High Volume Manufacturing Research Committee (HVM-RC), where he is Co-Chair of the Factory Information & Control Systems Subcommittee and also serves as an International Research Consultant for Intel Higher Education.

His experience prior to Intel includes Chief Software Architect for Flight Software at the NASA Lewis Research Center and Senior Project Management roles in the aerospace and automotive industries.

Presentation Title Connecting the Real World to the Digital Backbone – RFID and Wireless Sensor Networks Presenter Name Richard A Tyo, P.E. Job Title Principal Architect (ESS)

Abstract:
Evolving generations of computing applications are leveraging advances in sensor technologies - RFID and wireless sensor technologies in particular, to provide advanced computing capabilities that are driven by real-time physical events and the condition of the physical environment.

This presentation will address research and architectural challenges that arise while attempting to connect the real-world environment with computing infrastructures, while emphasizing the importance of deriving information from data. It will focus on the use of self-configuring distributed wireless sensor and effector networks to enable pervasive, autonomous, and occasionally-connected computing, such as will be required to support autonomous agents and complex monitoring and control systems.

Practical current examples will be discussed to illustrate some of the challenges, including discussion of RFID asset tracking systems used in the manufacturing and retail supply chains as well as occasionally-connected distributed wireless sensor network systems currently being used for monitoring in-transit shipments of goods via ocean shippers.

Researchers will be encouraged to develop new approaches to improve upon current techniques and to identify entirely new opportunities, especially in topics relevant to Intel.

Senior Engineer – Failure Analysis
Quality and Reliability Group – Philippines (CV Q&R)

Ruby graduated with a Ph.D. degree in Physics from the University of Bonn, Germany last 2005 and is a Senior Engineer in Failure Analysis, Quality and Reliability Group at Intel. Her Ph.D. research is on Laser Cooling and Laser Spectroscopy of Indium Atoms. Prior to graduate studies, she worked with Intel for four years in Failure Analysis and Assembly Integration. She was part of the cartridge product start-up team in 1996, and transferred the failure analysis capability from Assembly-Test Development (ATD) in Chandler to the Philippine HVM site. In the Quality and Reliability Group (Q&R), she is currently responsible for identifying and solving fab-related yield and quality issues, along with a team of test and yield engineers at the CV Assembly-Test site. Ruby is working on utilizing Atomic Force Microscopy for identifying device-related defects, and enabling parametric testing for new products. She is also involved in the Higher Ed Council and collaborates with Philippine universities to apply researches on optics and material science to failure analysis.

Presentation Title Failure Analysis: Solving Real-world Failures using Acoustics, Optics and Electron Beams Presenter Name Ruby dela Torre, Ph.D. Job Title Senior Engineer – Failure Analysis

Abstract:
Continuous scaling of microprocessor devices poses new challenges on their fabrication, test and failure analysis. As the dimensions of package-to-die interconnects, die-level contacts, and transistor gates decrease, the probability for electrical failures increases. The difficulty of localizing and imaging the defect also increases.

An overview of the current tools in failure analysis will be given, from localizing electrical failures to identifying the actual defect. Failure analysis tools are products of researches in imaging optics, acoustics, infrared spectroscopy, atomic force microscopy (AFM), and electron beam microscopy. Applications of these technologies in locating and imaging semiconductor failures will be discussed. Examples will be given, such as how acoustic waves can detect failures hidden under several layers of metal, and how the cause of submicron cracks is identified. The limitation of these analytical tools will be mentioned and will serve as spring-board for discussing new ideas and researches for enhancing the failure analysis capability in the semiconductor industry.

Intel Principal Engineer – ATM Process Control Systems
Assembly Operations, ATM

Nik has worked in Intel for 19 years and holds a B.Sc. degree in Mechanical Engineering. He has held various positions in Assembly and Test engineering both in technology development groups and high volume operations factories. He has led numerous technology transfer initiatives that were instrumental in the start up and launch of Intel’s flagship microprocessor products. In early 2006, he was appointed Intel Principal Engineer as a result of his work in the last 3 years shaping Process Control Systems (PCS) in Intel’s worldwide Assembly/Test factories. Nik recently returned from the US after a 2 year collaborative effort with the Assembly Technology Development group in Chandler, Arizona in the design, development and deployment of enhanced PCS capabilities.

Presentation Title Advancing Process Control Systems in Assembly/Test Manufacturing Presenter Name Nik Zurin Job Title ATM Principal Engineer

Abstract:
In the last 15 years, Intel Assembly/Test (A/T) has concentrated on output velocity as their primary goal. The rate of progress in developing and sustaining effective Process Control Systems (PCS) has not kept up with advances in factory output capability. This has led to an increasing gap in A/T’s ability to detect, contain and ultimately prevent excursions resulting in excessive yield losses and quality escapes to customer. The problem is further amplified with increasing complexity due to silicon-package interactions, materials and assembly processes with the introduction of new packaging technologies. In a deliberate effort to reverse the trend, a series of projects were undertaken to deliver enhanced and scalable PCS capabilities to meet A/T’s immediate and future requirements.

In responding to this call for action, a holistic and integrated PCS strategy was developed to:

1. Develop high precision metrology for engineering process monitors.
2. Deliver breakthrough data automation systems for online and offline PCS.
3. Establish a high performance PCS culture on the factory floor through People Programs.
4. Define and apply new statistical based methods to strengthen engineering basics on PCS.

During definition, module engineering used factory excursion data to identify areas of vulnerability in assembly. As a result, 83 key process parameters were singled out for improved process control. This included new metrology development and real time process monitors for better signal detection at root cause. Another major change introduced was the station controller with SPC++ to automate data acquisition for inline process monitors and improve end-of-lot statistical analyses. The new architecture significantly improves over the current work stream based system by:

Enabling in-line process monitors to detect and respond to process anomalies real time. ›

Removing possibility of human error and improving data integrity through automation.

To complement the engineering and automation solutions, a parallel effort was undertaken to establish a strong PCS culture on the factory floor. The People Systems program was aimed at producing unskilled factory operators with sound PCS basics in terms of out of control response, lot disposition & improved overall floor sensitivity to quality. Emphasis was on management support, communication, training and recognition to ensure this culture is sustained and ingrained with equal importance to factory output.

Finally, new statistical based methods were developed and applied to strengthen engineering basics. The direct outcome of this exercise led to a systematic approach for defining process targets and control limits, adoption of new PCS health metrics and a commitment to a disciplined PCS data review process.

The project team has been successful in achieving its objectives of delivering enhanced capabilities and creating a cultural shift. This presentation will describe the foundational changes that have been made in engineering, automation and people for PCS and how this effort marks the beginning of an exciting transformation of microprocessor assembly in Intel.

Director
Assembly Technology Development in Malaysia (ATD-M)

Kin graduated with a degree in the Bachelor of Science in Materials Science with upper second class honours in 1979 from University of Bath, UK. He joined Intel Malaysia in Oct. 1979 as an rcg and started work as quality assurance engineer in assembly. In 1983 he moved on to become the assembly plastic engineering manager. In 1986 he was on a 9 months assignment to Intel component q&r in Stellar Park, USA. In 1986 he returned as overall assembly qa manager then in 1987 progressing to become overall assembly and test qa manager for Malaysia site. In 1989 Kin joined ATD in PPTD(Penang Package TD) as a platform manager. In 1994 he progressed to head the overall PPTD dept till current position of ATD-M. He also published 2 papers; The Mighty Micro - a paper describing the integrated circuit and its significance wrt miniaturisation of transistor functions and it's assembly; Tapping 2000 Minds - a paper describing the method employs to get quality improvement participation from grassroot level via suggestion system. He also holds one USA patent on 'Recessed Marking on Ceramic Lid'.

On the soft side Kin has a wife, YY Ong and 3 great kids(Gan Suiji, a 24 yrs old daughter, still in university; Gan Yun Han, a 21 yrs old son and Gan Ji Yun, the youngest daughter at 18 yrs of age. Hobby wise - loves reading, photography and traveling.

Presentation Title Assembly Packaging: Bridging Silicon and Systems Presenter Name Kin Gan Job Title Director of Assembly Technology Development in Malaysia (ATD-M)

Abstract:
While you were surfing the Internet, playing your games or working on your project, did you ever wonder how are the microchips in your computers are manufactured? How are these microchips being processed? What are the materials used to obtain a robust package? What are the thermal solutions for the high performance devices? Wonder no more! This paper answers these questions and explains the assembly packaging of advanced microchip. The challenges and trends of high density interconnection (HDI) of the semiconductor industry based on Moore’s Law is also discussed in this paper. It also considers the challenging trends of increasing transistor numbers, I/O counts, electrical power and thermal generations. In general, the impacts of Moore’s Law are the reduction in package dimensions, enhancement in microchip features and increment of package complexity. In an attempt to provide an insight on how materials affect the performance electronic packages, this paper discusses on topics such as Intel lead-free roadmap, robust interconnection solder and efficient thermal interface materials for heat management. You will discover the use of dual/multi-core to enhance and accelerate end user performance. If you are interested to learn more, come and join us on the discussion of the challenges and trends of semiconductor packaging!