Included on this Page:

Dr. Maria Bezaitis Mr. Shekhar Borkar Mr. Ajay Bhatt Dr. P. Geoffrey Lowney Dr. Ian Young

Director, People & Practices Research
Intel Research

Maria Bezaitis is Director of the People and Practices Research Lab within Intel Research. In this role, Maria leads the team of social scientists who conduct ethnographic research on people, practices and the institutions that govern everyday life. Current research programs include a focus on driving adoption in low-infrastructure communities, time & mobility, everyday monetary practices, and Islamic charitable institutions.

Maria comes to Intel with over 10 years experience leading and managing ethnographic research organizations. She was Vice President at Sapient Corporation where she was responsible for the Advanced Research Team that focused on developing research-based offerings for key business units. Maria began her professional career at E-Lab, a consultancy that pioneered the use of ethnography for product development, brand and business innovation. At E-Lab she was a managing partner and had oversight of E-Lab’s project practice. Maria completed her Ph.D. in French Literature and Cultural Studies at Duke University where she focused on early image technologies, “collections” and seriality. She is based in Oregon on the Amber Glen campus.

Presentation Title Intel Research: A Vision for Innovation Presenter Name Maria Bezaitis Job Title Director, People & Practices Research Intel Research

Abstract:
Intel Research is focused on a vision of Essential Computing: simplifying and enriching all aspects of work and daily life through application and system technologies that collectively empower individuals, connect them to each other and into the fabric of networking society. This vision encompasses five research themes. The themes—Personal Awareness, Rich Communication, Physicality, Concealing Complexity, and Emergence Engineering—focus on technologies which can enrich our lives by increasing their awareness of human activities and goals, and becoming more essential and seamless parts of our lives.

In order for new technologies to be compelling and accepted, they require the right blend of capabilities combined with appropriateness for the environment to create both excitement and real value for the intended user. To achieve Intel’s vision of Essential Computing, we are fundamentally changing our research methodology, building multi-disciplinary teams that span Intel Research’s competencies in distributed systems and networking, computer architecture, wireless communications, software applications, machine learning, machine vision, ethnography, sociology, people and practices, and emerging regions.

People & Practices Research is one of the 4 labs that comprise Intel Research. Our research agenda ensures that Intel Research will continue to provide leadership on how to keep innovative research on technology intimately tied to what matters to people and everyday experience. Our strategy is to work with universities and academics on research programs that "disrupt" Intel's assumptions about what matters to people.

Intel Fellow
Director, Microprocessor Research
Microprocessor Technology Lab

Shekhar Borkar graduated with MS in Physics from University of Bombay, MSEE from University of Notre Dame in 1981, and joined Intel Corporation. He worked on the 8051 family of microcontrollers, the iWarp multi-computer project, and subsequently on Intel's supercomputers. He is an Intel Fellow and Director of Microprocessor Research. His research interests are high performance and low power digital circuits, and high-speed signaling. Shekhar is an adjunct faculty member at Oregon Graduate Institute, and teaches VLSI design.

Presentation Title Extending and Expanding Moore’s Law — Challenges and Opportunities Presenter Name Shekhar Borkar Job Title Intel Fellow; Director, Microprocessor Research

Abstract:
Moore's Law was responsible for five orders of magnitude VLSI system performance increase in the last three decades. Technology scaling improved transistor performance, increased frequency, increased integration capacity to realize complex architectures, and reduced energy to keep power dissipation within limit. Moore's Law will continue for years to come, providing billions of transistors; however, power, energy, variability, and reliability will be the barriers. Performance at any cost will not be an option in the future; VLSI systems will have to emphasize performance delivered in a given power envelope, with complexity limited by energy efficiency, variability and reliability. This talk will discuss potential solutions in process technology, circuits, and micro architectures to exploit future gigascale integration capacity. The system on a chip (SOC) concept will help integrate diverse functional blocks, providing valued performance and reliability. The talk will conclude with recommendations to the VLSI system designers on how to exploit these emerging paradigms.

Intel Fellow
Digital Enterprise Group
INTEL CORPORATION

Ajay Bhatt is an Intel Fellow in the Digital Enterprise Group and director of the Platform & Interconnects Architecture. Bhatt is responsible for future platform and interconnects directions. This role involves coordination of platform architectures and technologies across the market segments both internally and with the industry. Bhatt's primary focus areas are platform partitioning, I/O and interconnects technologies.

At Intel, Bhatt has been instrumental in driving definition and development of broadly adopted technologies such as the Universal Serial Bus (USB), Accelerated Graphics Port, PCI Express, Platform Power management Architecture and various chipset enhancements. Bhatt joined Intel in 1990 as a senior staff architect for Chipset Architecture team in Folsom.

Bhatt received his bachelor’s degree in electrical engineering from the M.S. University, Baroda, India, in 1980. He received his master’s degree from The City University of New York in 1984. Bhatt holds nine U.S. patents with three more patents pending.

In 1998, 2003, and 2004 Bhatt was nominated to take part in a Distinguished Lecture Series at leading universities in the United States and Asia. He received an Achievement in Excellence Award for his contribution to PCI Express Specification Development in 2002. Bhatt is PCI Express Steering Committee chair at the PCI-SIG.

Quick Facts

Director of Platform and I/O Interconnects Architecture in the Desktop Enterprise Group ›

Responsible for platform architecture, I/O technologies and interconnects

Presentation Title The New Era of Computing Presenter Name Ajay Bhatt Job Title Intel Fellow

Abstract:
Leaping from GHz era to today’s Energy Efficient Performance, Intel’s Core Microarchitecture marks the beginning of a new era of computing. In this talk, Intel Fellow Ajay Bhatt will provide an in-depth discussion how Intel will lead the industry in breaking through the sound barrier of entering Terascale computing, Petascale computing and beyond through platforms with multi-threaded Intel processor cores.

Intel Fellow, Digital Enterprise Group
Director, Compiler and Architecture Advanced Development
INTEL CORPORATION

P. Geoffrey Lowney is an Intel Fellow, Digital Enterprise Group and Director of Compiler and Architecture Advanced Development. He is responsible for using advanced compiler technology to improve the performance and usability of Intel Architecture processor family products.

Lowney joined Intel as part of a June 2001 agreement with Compaq Computer Corporation that called for the transfer of microprocessor engineering and design expertise to Intel.

Prior to joining Intel, he was a Compaq Fellow and Director of Compiler and Architecture Development for the Alpha Microprocessor Group. His responsibilities included developing compiler technology and tuning compilers for Alpha systems, providing architectural direction to the microprocessor design teams and designing Alpha architecture extensions.

Before joining Digital Equipment Corporation in 1991, Lowney was a Consulting Engineer at Hewlett-Packard from 1990 to 1991. From 1984 to 1990, he was Director of Compiler Development at Multiflow Computer.

Lowney received his doctorate and master's degrees in computer science and his bachelor's degree in mathematics from Yale University in 1983, 1978 and 1975, respectively. He holds 11 patents in computer architecture and compiler technology.

Presentation Title Software for multi-core processors. Presenter Name P. Geoffrey Lowney Job Title Intel Fellow, Director, Compiler and Architecture Advanced Development

Abstract:
Future processors developed by Intel will have more than one core on a die. Multi-core processors will bring tremendous computing power to the desktop PC, enabling new classes of applications. These applications will be written using parallel programming techniques. In this talk I will present some parallel applications Intel is researching in China. I will discuss the parallel programming model for a multi-core processor and identify new opportunities and challenges for software. I will also discuss how multi-core processors will be used in modern dynamic programming environment.

Senior Fellow and
Director of Advanced Circuits and Technology Integration
Logic Technology Development
Technology and Manufacturing Group

Ian Young was born in Melbourne, Australia. He received the B. Eng. and M. Eng. Science degrees in electrical engineering from the University of Melbourne in 1972 and 1975, respectively. He received the Ph.D. degree in electrical engineering from the University of California, Berkeley, in 1978, where he was one of the pioneers of the switched capacitor filter in MOS technology.

In 1983, he joined the Technology Development group at Intel Corporation in Hillsboro, Oregon, where he is currently an Intel Senior Fellow and Director of Advanced Circuits and Technology Integration. He is responsible for developing future circuit design techniques as well as optimizing the manufacturing process technology for both microprocessor and communication product implementations. He has made contributions to the design of CMOS DRAMs, CMOS SRAMs, microprocessor and communications process technology development and circuit design, and the design of Phase Locked Loops for microprocessor clocking and input/output (I/O).

The current focus of his work is mixed-signal circuits for high speed serial I/O links for microprocessors and chip sets, mixed-signal RF CMOS circuits for wireless communications and research into optical I/O for off-chip interconnects.

Dr. Young was a member of the Program Committee for the Symposium on VLSI Circuits from 1991 to 1998, serving as the Program Committee Co-Chair/Chairman in 1995 and 1996, and the Symposium Co-Chair/Chairman in 1997/1998. He was a member of the International Solid-State Circuits Conference (ISSCC) program committee from 1992 to 2005, serving as the ISSCC Digital Subcommittee Chairman from 1997 through 2003, ISSCC Technical Program Vice-chair in 2004 and Chair in 2005.

Dr. Young is an IEEE Fellow. He holds 40 patents.

Presentation Title Intel’s Silicon Technology R&D Pipeline Presenter Name Ian Young Job Title Senior Fellow and Director of Advanced Circuits and Technology Integration

Abstract:
Ian Young will talk about silicon technology as the foundation on which Intel chips and platforms are built. Intel has a silicon research and technology pipeline that produces a new process technology every two years, in accordance with Moore's Law. Ian will describe the current 90 nm and 65 nm process technologies, and the features being developed for 45 nm and future generations.