Select a location for
Intel Education
Home ›Intel® Education Initiative › India Faculty ›
India Faculty
Prof. H. S. Jamadagni

Prof. H. S. Jamadagni is a Ph.D. from the IISc. - Bangalore. He is currently the Chairman of the Centre for Electronics Design and Technology. He has published many papers and research publications. He is the force and the key driver for the Intel Internet Exchange Architecture® Program in India. He is one of the key mentors for the Intel Higher Education program in India and was the program coordinator for various Intel workshops and research programs.

Prof. H. S. Jamadagni’s key interest areas are Embedded Systems and VLSI for Wireless Networking. Apart from the same he expertise lies in IXA Platform, Computer Architecture & Microelectronics. He is a teacher, product developer, researcher, industrial consultant and one of the main coordinators of the national education publications in India a mentor to many a research student.

Institution Name Indian Institute of Science – Bangalore
Telephone +91 – 80 – 22932966 / 23600808
  • Optimal call admission control in generalized processor sharing (GPS) schedulers - Nandita D., Joy Kuri and H.S. Jamadagni - Proceedings of IEEE INFOCOM - 2001.
  • Issues in Packaging Technology for High Performance Computing - H.S. Jamadagni, G.V. Mahesh, G. Ananda Rao and E.S. Dwarakadasa - ADCOMP '95 - Bangalore - December 20-22 - 1995.
  • A New Technique for Improving Quality of Speech in Voice over IP Using Time-Scale Modification - Samar Agnihotri, K. Aravindhan, H.S. Jamadagni, and B.I. Pawate - Proceedings IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2002) - Orlando, Florida.
Dr. S. Jayaraman
Date of Birth and Age 13-02-1951, 55 Years
Profession and Designation Professor & Head, ECE Department
PSG College of Technology, Coimbatore – 4
Academic Qualifications B.E.(ECE) 1974 - PSG College of Technology, Coimbatore
M.E.(Comm. Systems) 1976 - PSG College of Technology, Coimbatore
Ph.D. (DSP) 1993 - PSG College of Technology, Coimbatore
Experience Teaching 30 Years
Period Institution
1976 - 1980 Siddaganga Institute of Technology, Tumkur, Karnataka, India
1980 – till date PSG College of Technology, Coimbatore, India
Research Experience Successfully guided one scholar for Ph.D. and currently guiding 4 scholars for Ph.D.s
Research Interests Image Compression beyond Wavelets, Stability analysis of Multi Dimensional Systems, Non-Linear Signal Processing
Publications Over 30 International and National Journal publications
Over 40 International and National Conferences
Professional Bodies Member of IEEE, Life Member of Indian Society of Technical Education, System Society India and member of Institution of Engineers India
Other Interests Classical Music & Pedagogy based Training
Activities Currently Engaged Authoring books on:
  • Signals & Systems to be published by Pearson Education
  • DSP to be published by TATA McGraw-Hill
Dr. Madhu Mutyam

Dr. Madhu Mutyam received Ph.D. from IIT Madras in 2003 and joined IIIT Hyderabad as an Assistant Professor. His research areas include architectural solutions to power, performance, and reliability issues in VLSI systems targeting superscalar, multi-core, and VLIW processors in both normal conditions and process variation conditions. He is a recipient of BOYSCAST fellowship from the Department of Science and Technology, India, for the year 2004-05. On this fellowship, he spent one year in the Microsystems Design Laboratory, Department of Computer Science and Engineering, Pennsylvania State University, exploring several research topics targeting superscalar and VLIW processors. He is currently working on several projects related to low-power and high-performance VLSI design. He is a professional member for ACM and IEEE. He is a reviewer for ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on Very Large Scale Integration Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and several international conferences related to architecture and VLSI.

Institution Name International Institute of Information and Technology - Hyderabad
Selected Publications
  • K. Najeeb, V. Gupta, Madhu Mutyam, and V. Kamakoti. Temporal redundancy based encoding techniques for peak power and delay reduction of on-chip buses. Journal of Low Power Electronics . Accepted.
  • Madhu Mutyam, F. Li, N. Vijaykrishnan, M. Kandemir, and M.J. Irwin. “Compiler-directed thermal management for VLIW functional units”. Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES’06), Ottawa, Canada, June 14-16, 2006, ACM SIGPLAN Notices, pp. 163-172. (Selected as one of the best papers in the conference to publish in the ACM Transactions on Embedded and Computing Systems journal.)
  • K. Najeeb, V. Gupta, Madhu Mutyam, and V. Kamakoti. “Delay and peak power minimization for on-chip buses using temporal redundancy”. 16th ACM Great Lakes Symposium on VLSI (GLSVLSI’06), Philadelphia, April 30 – May 2, 2006.
  • Madhu Mutyam, M. Eze, N. Vijaykrishnan, and Y. Xie. “Delay and energy efficient data transmission for on-chip buses”. IEEE Computer Society Annual Symposium on Emerging Technologies and Architectures (ISVLSI’06), 335-360, 2006.
Prof. N. S. Murthy
Personal Details Citizenship Indian National
Passport No. V-404816 issued at Hyderabad
dated 13-10-1995
Present Address Dr. N.S.Murthy, Professor and Head,
Dept. of ECE,
National Institute of Technology,
Warangal – 506004, India.
Permanent Address Peruru, Amalapuram Taluk,
East Godavari district, - 533218, AP.
Marital Status Married (status: wife and two sons – studying).
Educational Qualifications B.E. (1972) Electronics and Communications Engineering, Govt. College of Engineering, Kakinada (AP) - 533003, India.
M.S. (1982) Digital Systems, EE Department, Indian Institute of Technology, Madras, India.
D.I.I.Sc. (1983) Electronics Design, CEDT, Indian Institute of Science, Bangalore, India.
Ph.D. (1999) Department of ECE, National Institute of Technology, Warangal, India.
Academic Activities and Experience Present Head of the Department of ECE, responsibilities include managing the UG and PG Courses, revising the curriculum, administration, implementing various projects sanctioned by different agencies, teaching UG and PG courses and handling their projects, guiding B.Tech., M.Tech. and Ph.D. students and carrying out research.
1985-90 Faculty and Visiting Professor, Garyounis University and Bright Star Universities of Technology, Benghazi and Brega, Libya.
1974-85 Scientific Officer (Engineer) SC and SD, at the Reactor Research Centre, Kalpakkam (presently Indira Gandhi Centre for Atomic Research), India. Involved in the design and development of Nuclear Instrumentation modules and systems.
Courses taught during the last 5 years: (both for B.Tech. and M.Tech.)
  • Device Modeling and Analog IC Design
  • VLSI System Design
  • Microprocessor and Microcomputer Systems
  • Digital IC Design
  • Electronic Instrumentation
  • VLSI Architectures
  • Digital Signal Processing
  • Neural Networks
  • Biomedical Instrumentation
  • Related Labs
Research Activities
  • Low Power VLSI Architectures for DSP Applications
  • VLSI Interconnect models and noise reduction in DSM regime
  • ASIP Implementations (FPGA based)
  • Higher Order Spectral Analysis (DSP)
Important Projects undertaken
  • Coordinator for the Research Project “Studies on Modeling and Noise Reduction in VLSI Interconnect Structures in the DSM Regime”, sponsored by the MHRD, Govt. of India – on going
  • Coordinator for the Special Manpower Development in the area of VLSI and related Software (SMDP_VLSI) project sponsored by the Ministry of Communication and IT, Govt. of India – on going
  • Principal Investigator for the Research Project (“Study and Simulation of Smart Jamming Techniques..”) sponsored by the Defence Electronics Research Labs, DRDO, India. – on going
  • Coordinator, UK-India RECs Project sponsored by the Governments of UK and India (1994-98)
  • Coordinator/Principal Investigator for TWO projects (Setting up of Programmable Logic Design Lab and Intelligent Instrumentation Lab) sponsored by the MHRD and AICTE in the Thrust areas
M.Tech./M.Tech. (Research) / Ph.D. Theses supervised
  • Guided around 20 M.Tech / (Res) projects
  • Guiding two Ph.D. candidates
  • Examined more than 20 M.Tech and 5 Ph.D theses of different universities and NITs
  • Question Paper Setter for JNTU, OU, BITS, Anna University, Andhra University and Sri Venkateswara University
Memberships and Other Activities
  • Reviewer for the Journal of Atmospheric Science Letters (ASL), U.K.
  • FIETE: Fellow of Institute of Electronics and Telecommunication Engineers, India.
  • LM (ISTE): Life Member of Indian Society for Technical Education, India.
  • Chairman, Board of Studies, ECE Department, NIT, Warangal, India.
  • Chairman, Board of Studies, ECE Department, Kakatiya Institute of Technology and Science, Warangal, India.
  • Member, Board of Studies, Department of ECE, JNTUCE, Hyderabad.
  • Member, BOS, Gandhi Institute of Technology and Management, Visakhapatnam, AP.
  • Member, Recruitment and Assessment Board, DRDO, New Delhi.
  • Member, Faculty Selection Committee, JNTU, Hyderabad.
  • Resource person for various seminars / workshops conducted by many engineering colleges in the state.
  • Member, Selection Board (Japanese Scholarships), MHRD, Delhi.
Seminars/ Workshops/ Conferences conducted – attended
  • Conducted two short term courses for the engineering college teachers in the areas of DSP and VLSI
  • Conducted more than half a dozen workshops (two – three day duration) in the areas of VLSI and Information Technology during the UK-India RECs project
  • Attending International Conferences on VLSI being held every year in India as a Fellow (Fellowship granted by the conference secretariate every year)
  • Attended VLSI Design and Test Workshops two times (List of recent publications enclosed)
Collaboration with Industries/R&D organizations
  • Sponsored Research Projects in the areas of DSP and VLSI in collaboration with DRDO and Ministry of IT, Govt. of India.
  • Collaborating with Innovative Communication Systems, Hyderabad in industrial R&D
  • Collaborating with BARC, ANURAG, IGCAR, CDAC, ISRO and Private Organisations like ACL, ICS, Hyderabad for M.Tech projects
Other Interests Yoga Research and Applications
  • Prof. J. Srihari Rao, Dean (Academic Affairs), National Institute of Technology, Warangal – 506004, India.
  • Prof. S.Srinivasan, Chairman, Dept. of Electrical Engg; Indian Institute of Technology, Madras, Chennai - 600036.
  • Prof. K.Kishan Rao, Principal, Kakatiya Institute of Technology and Science, Warangal, India.
Prof. S. K. Nandy

Prof. S. K. Nandy holds Ph.D. from IISc., Bangalore and is a professor at the Super Computer Education and Research Centre at IISc. Bangalore. He was the Convener of the CAD Lab at IISc.

University Super Computer Education and Research Centre
Indian Institute of Science – Bangalore
Research Interests
  • Application Specific Instruction Set Processor (ASIP) Architecture: Design, analysis and development of computational structures targeted for embedded systems on silicon.
  • Reconfigurable High Performance Processor Architectures: Design, evaluation and synthesis of processor architectures from parameterized computational structures to meet performance requirements of current day applications on portable and hand held systems.
  • Systems on Silicon: Application of hardware-software co-design techniques to explore architecture-algorithm design space, and realization of various architectures from within a single framework.
  • Compiling Techniques for Low Power: Compiler optimizations and retargettable code generators for low power.
  • Architectural Synthesis of High Performance VLSI Systems: Design and development of an architecture evaluator. Issues involve study and analysis of various mapping and scheduling schemes.
  • Parallel/Pipelined low latency, high throughput arithmetic unit architectures: Performance-driven multiplier architectures and multiplication algorithms.
  • Multi-threaded Architecture: Design and development of a multi-threaded architecture for media applications.
  • Global Shared Memory Cache Coherence Protocols: Compiler assisted directory-less shared memory cache coherence protocol for distributed shared memory systems.
Prof. Rajat Moona
Department Computer Science and Engineering
Institution Name Indian Institute of Technology – Kanpur
Country/Region India
Telephone +91 – 512 - 2597692
Personal Background Prof. Rajat Moona is a B.Tech. in Electrical Engg. from IIT Kanpur from 1981-85 and did his Ph.D. program at Indian Institute of Science in Bangalore from where he graduated in 1989. He has worked for little more than one year in IISc. Bangalore in the Supercomputer Education and Research Centre immediately after his Ph.D. and joined IIT Kanpur in the beginning of 1991.
Study Field His areas of research interest and teaching are Computer Architecture, VLSI Design, Operating Systems and Embedded Systems.
Few of his patents include:
  • Rajat Moona, B.V. Kumar, S.V. Subramanya, "Authentication using Non-Biometric and Biometric Information". Indian and US Patent applied for.
  • Rajat Moona, Russell Klein, "Compiling memory dereferencing instructions from software to hardware in an electronic design". Indian and US Patent applied for.
  • Rajat Moona, R. Gopalakrishnan, Russell Klein, "Area optimization of hardware for algorithms by optimizing sizes of variables of the algorithm". Indian and US Patent applied for.
  • Rajat Moona, Russell Klein, "Repartitioning performance estimation in a hardware-software system." US Patent No. 6856951.
  • K.A. Padmanabhan, Rajat Moona, Rohit Toshniwal, Bipul Parua "Portable computer printer". Indian Patent 1521/Del/99.
Dr. Ranjani Parthasarathi
Department Computer Science and Engineering Department
Institution Name College of Engineering – Guindy, Chennai
University Anna University
Field of Specialization
  • Computer Architecture
  • Re-configurable Computing
  • Computer Networks
  • Network Processors
  • Embedded Systems
Academic Qualifications
  • Ph.D. (Computer Science & Engineering)
  • M.S. (Computer Science & Engineering
  • B.E. (Electronics and Communication)
  • Shanthi A.P. and Parthasarathi R. (2005), ‘Genetic Learning Based Fault-Tolerant Models for Digital Systems’, International Journal on Applied Soft Computing (ASoC), Elsevier Publishers, Vol. 5, Issue 4, July 2005, pp. 357-371.
  • Shanthi A.P., Karthik S.L. and Parthasarathi R. (2005), ‘Evolution of Asynchronous Sequential Circuits’, Proceedings of the 7th NASA/DoD Conference on Evolvable Hardware (EH’05), Washington, DC, USA, IEEE Computer Society Press, July 2005, pp. 93-96.
  • Shanthi A.P. and Parthasarathi R. (2004), ‘Towards Evolving Wearable Surrogate Devices’, Proceedings of the Workshop on Knowledge Discovery in Biomedicine, 8th Pacific Rim Conference on AI, New Zealand, November 2004, pp. 125-134
  • Mohan G Kabadi and Ranjani Parthasarathi, “Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache subsystem”, International Conference on Advanced Computer System Architecture Conference (ACSAC), September 2003.
E-mail Address
Prof. Sanjeev Kumar Aggarwal
Department Computer Science and Engineering
Institution Name Indian Institute of Technology – Kanpur
Country/Region India
Telephone +91 – 512 - 2597614
Pesonal Background Sanjeev K Aggarwal is with the Department of Computer Science and Engineering at IIT Kanpur where he was the head of the department during Aug 2002 - Dec 2005. He has about twenty years of research and teaching experience in the area of Compiler Design. For his PhD thesis, he worked on Automatic Code Generation problem and developed a frame work for retargetable code generation (advisor Professor Vishv M Malhotra). This work was later used in industrial compilers. He has published extensively in international forums and has handled a large number of industry/government funded projects.

He worked with Tata Research Development and Design Centre, Pune from 1986 to 1990. At TRDDC he was project leader for CHILL compiler suite which was developed for C-DOT's digital switches. The project involved development of highly optimizing CHILL compilers and debuggers. This was a large project involving about 12 programmers over a period of three years. He has hands on experience with compiler development, testing and project management.

Study Field His areas of research interest are Grid Computing, High Performance Computing, Compilers for High Performance Architectures, Compiler Design, Code Optimization, Code Generation, and Application of Language Processing Technology in Tools for Software Engineering. He has been teaching courses on Grid Computing, Compiler Design, Compilers for High Performance Architectures, and Programming languages.

Prof. Sanjeev’s Teaching interest lies in courses on Grid Computing, Compiler Design, Compilers for High Performance Architectures, and Programming languages.

Dr. M. P. Sebastian
Department Computer Science and Engineering
Institution Name National Institute of Technology – Calicut
Country/Region India
Telephone +91 – 495 – 2286800
Personal Background Dr. M. P. Sebastian holds a B. Tech. in Electronics and Communication Engineering from University of Kerala, Trivandrum and holds a Master of Engineering (M.E) in Computer Science from Indian Institutes of Science, Bangalore. Dr. Sebastian did his Ph.D from Indian Institute of Science, Bangalore on Interconnect Networks for Parallel Computers. He has interaction with Intel on Intel Planet Lab, Curriculum Development & Research.
Study Field His areas of research interest and teaching includes Cryptography, Computer Architecture, Computer Networks & Interconnection Networks with focus on Network Security, Computer Architecture, Mobile Networks.
Few of his research publications are:
  • M. P. Sebastian, P. S. Nagendra Rao, and Lawrence Jenkins, "Properties and performance of folded cube-connected cycles," Journal of Systems Architecture (Elsevier - North Holland), Vol. 44, pp. 359-374, 1998.
  • Ahmed Siraj and M. P. Sebastian, "Achievable Maximum Throughput and Coverage Range of Wireless LANs," Journal of Computer Science (JCS), Vol 1, No.1, pp 1-7, August 2005.
  • M. P. Sebastian, P. S. Nagendra Rao, and Lawrence Jenkins, “Topological Properties of the CCCF Graph," Journal of CSI, Vol 35, No.4, pp. 25-28, October- December 2005.
Prof. G. N. Srinivasa Prasanna, Ph.D. (MIT)
Education B.Tech at IIT - Kanpur
MS and Ph.D at MIT, USA.
Work Experience He has worked at Lucent Microelectronics and Lucent Bell Laboratories, for about 11 years. At Lucent he worked in a variety of fields, including VLSI, switching, optical networking etc. He was responsible for the signal processing system design of a major access product for Lucent’s 5ESS switch, accounting for 30 million lines worldwide.
Research Interests Prof. Prasanna is interested in communication systems (optical, wireless, powerline), robust optimization, electromechanical systems, animation and mathematics.
Recently his research interests have included optical networking and robust optimization. He has published about 35 papers, and holds about 15 patents. He has been on several technical program committees and has served as a referee for several journals.
Ms. Suchismita Roy
Institution Name National Institute of Technology, Durgapur, West Bengal, India.

Bacheclor of Engg., Computer Science and Engg. from National Institute of Technology, Rourkela. 1994.

Master of Technology, Computer Science and Engg. from Indian Institute of Technology, Bombay. 1996.

More than 10 years of teaching experience in Computer Science and Engg. at National Institute of Technology, Rourkela and National Institute of Technology, Durgapur.

Courses taught include Algorithm Analysis and Design, Computer Networks, Distributed Systems, Testing and Verification of VLSI Systems, Computer Organisation and Object Oriented Programming.

Currently registered for Ph.D. at Indian Institute of Technology, Kharagpur under the supervision of Dr. P.P.Chakrabarti, Professor in Computer Science and Engineering.

Research Interests include Testing and Formal Verification of VLSI Circuits, Validation and Performance Analysis of Gate Level VLSI Circuits, Boolean Satisfiability based Modeling and Simulation.

Research Publications
  • Bounded Model Checking for OpenLTL.
    S.Roy, P.Dasgupta and P.P.Chakrabarti
    IEEE International VLSI Design and Test Symposium (VDAT) 2005.
  • Satisfiability based Solutions for Consistency Problems in Open System Specifications.
    S.Roy, S.Das, P.Basu, P.Dasgupta and P.P.Chakrabarti.
    IEEE/ACM International Conference on Computer Aided Design (ICCAD) 2005.
  • Bounded Delay Timing Analysis using Boolean Satisfiability.
    S.Roy, P.P.Chakrabarti and P.Dasgupta.
    IEEE/ACM International Conference on VLSI Design (VLSI) 2007.
Dr. B. Venkataramani
Department Department of Electronics & Communication Engineering
Focus Area FPGA and SOC based DSP system design, software defined radio
Activities with Intel Curriculum Development
Education Ph.D. from Indian Institute of Technology, Kanpur, 1995
Advisors Dr. Sanjay K. Bose and Dr. K.R. Srivatsan
M.Tech. from Indian Institute of Technology, Kanpur, 1984
B.E.(Hons) from Regional Engineering College, Tiruchirapalli, 1979
Professional Experiences Aug 1987 – till date Faculty of Electronics & Communication (ECE),
Presently Professor of ECE,
National Institute of Technology (NIT), Tiruchirappalli
Oct 1997 – May 2000 Head of Computer Support group,
Regional Engg. College (Presently known as NIT), Tiruchirappalli
Aug 1984 – Apr 1987 Research Engineer, Indian Institute Of Technology, Kanpur, India
Aug 1979 – July 1982 Deputy Engineer, Bharat Electronics Ltd., Bangalore, India
Research Publications
  • G. Seetharaman, B. Venkataramani and G. Lakshminarayanan, “Design and FPGA implementation of self tuned wavepipelined filters”, Transaction of IETE journal of research , vol.52, No.4, July-August, 2006, pp 281-286.
  • G. Lakshminarayanan, B. Venkataramani, “Optimization techniques for FPGA based wave-pipelined DSP blocks”, Proc. of IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol. 13, no. 7, July 2005, pp 783-793
  • G. Seetharaman, B.Venkataramani, V. Amudha, Anurag Saundattikar, “System on chip implementation of 2D DWT using lifting scheme”, Proc. of the International Asia and South Pacific Conference on Embedded SOCs (ASPICES 2005), July 5-8, 2005, Bangalore
  • G. Lakshminarayanan, B. Venkataramani, J. Senthil Kumar, A.K. Md, Yousuf, G. Sriram, M.S. Jambunathan, “Design and FPGA implementation of image block encoders with 2D-DWT”, Proc. IEEE TENCON 2003 , Bangalore, Oct 15-17, 2003, Vol III, pp 1015-1019
  • V. Amudha, B. Venkataramani, R. Vinoth kumar and S. Ravishankar, “SOC implementation of HMM based speaker independent isolated digit recognition” to be presented in International conference VLSI design to be held at Bangalore during 6-10 Jan 2007.
Personal Webpage
Dr. G. S. Visweswaran
Office Address Room No. II/302, IIT Delhi
Telephone +91 11 26591077
+91 11 26853607 (External)
Qualifications B. Tech. Madras University
M. Tech. BITS Pilani
Ph. D. IIT Kanpur
Research Area
  • Neural Networks.
  • CAD of VLSI.
  • Design of Digital, Analog and Mixed Signal VLSI Circuits.
Sponsored Projects
  • Project IMPACT SSS(RP01070)
  • Natsem India Design Pvt. Ltd.
  • IIT Delhi
  • ST Microelectronics Ltd.
  • Intel Corporation
  • Department of Electronics(GoI)